forked from luck/tmp_suning_uos_patched
ARM: integrator: merge PCIv3 driver into one file
The Integrator/AP PCI bridget, "v3" is contained in two files, where pci.c is a socket container to plug in the v3 device. However to transition the v3 to enable device tree probing, it need to be converted to a platform device (so that it can have a device node in the device tree) and then we want the PCI driver in a single file, as any other device driver, so we can handle variants using compatible strings and device name, and get the base address etc from resources connected to the device node. To move toward this goal we consolidate all code in the pci_v3.c file. Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
14d86e725e
commit
f4bc4f0ab4
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@ -106,9 +106,4 @@ extern struct pci_ops via82c505_ops;
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extern int via82c505_setup(int nr, struct pci_sys_data *);
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extern void via82c505_init(void *sysdata);
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extern struct pci_ops pci_v3_ops;
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extern int pci_v3_setup(int nr, struct pci_sys_data *);
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extern void pci_v3_preinit(void);
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extern void pci_v3_postinit(void);
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#endif /* __ASM_MACH_PCI_H */
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@ -8,5 +8,5 @@ obj-y := core.o lm.o leds.o
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obj-$(CONFIG_ARCH_INTEGRATOR_AP) += integrator_ap.o
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obj-$(CONFIG_ARCH_INTEGRATOR_CP) += integrator_cp.o
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obj-$(CONFIG_PCI) += pci_v3.o pci.o
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obj-$(CONFIG_PCI) += pci_v3.o
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obj-$(CONFIG_INTEGRATOR_IMPD1) += impd1.o
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@ -1,113 +0,0 @@
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/*
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* linux/arch/arm/mach-integrator/pci-integrator.c
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*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*
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* PCI functions for Integrator
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*/
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include <mach/irqs.h>
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/*
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* A small note about bridges and interrupts. The DECchip 21050 (and
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* later) adheres to the PCI-PCI bridge specification. This says that
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* the interrupts on the other side of a bridge are swizzled in the
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* following manner:
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*
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* Dev Interrupt Interrupt
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* Pin on Pin on
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* Device Connector
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*
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* 4 A A
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* B B
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* C C
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* D D
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*
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* 5 A B
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* B C
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* C D
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* D A
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*
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* 6 A C
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* B D
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* C A
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* D B
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*
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* 7 A D
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* B A
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* C B
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* D C
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*
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* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
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* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
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*/
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/*
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* This routine handles multiple bridges.
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*/
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static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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if (*pinp == 0)
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*pinp = 1;
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return pci_common_swizzle(dev, pinp);
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}
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static int irq_tab[4] __initdata = {
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IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
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};
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/*
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* map the specified device/slot/pin to an IRQ. This works out such
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* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
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*/
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static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int intnr = ((slot - 9) + (pin - 1)) & 3;
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return irq_tab[intnr];
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}
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extern void pci_v3_init(void *);
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static struct hw_pci integrator_pci __initdata = {
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.swizzle = integrator_swizzle,
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.map_irq = integrator_map_irq,
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.setup = pci_v3_setup,
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.nr_controllers = 1,
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.ops = &pci_v3_ops,
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.preinit = pci_v3_preinit,
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.postinit = pci_v3_postinit,
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};
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static int __init integrator_pci_init(void)
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{
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if (machine_is_integrator())
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pci_common_init(&integrator_pci);
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return 0;
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}
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subsys_initcall(integrator_pci_init);
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@ -35,6 +35,7 @@
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#include <asm/signal.h>
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#include <asm/mach/pci.h>
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#include <asm/irq_regs.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/pci_v3.h>
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@ -337,7 +338,7 @@ static int v3_write_config(struct pci_bus *bus, unsigned int devfn, int where,
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops pci_v3_ops = {
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static struct pci_ops pci_v3_ops = {
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.read = v3_read_config,
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.write = v3_write_config,
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};
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@ -471,7 +472,7 @@ static irqreturn_t v3_irq(int dummy, void *devid)
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return IRQ_HANDLED;
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}
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int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
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static int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
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{
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int ret = 0;
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@ -490,7 +491,7 @@ int __init pci_v3_setup(int nr, struct pci_sys_data *sys)
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* V3_LB_BASE? - local bus address
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* V3_LB_MAP? - pci bus address
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*/
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void __init pci_v3_preinit(void)
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static void __init pci_v3_preinit(void)
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{
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unsigned long flags;
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unsigned int temp;
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@ -589,7 +590,7 @@ void __init pci_v3_preinit(void)
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raw_spin_unlock_irqrestore(&v3_lock, flags);
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}
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void __init pci_v3_postinit(void)
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static void __init pci_v3_postinit(void)
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{
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unsigned int pci_cmd;
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@ -610,3 +611,82 @@ void __init pci_v3_postinit(void)
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register_isa_ports(PHYS_PCI_MEM_BASE, PHYS_PCI_IO_BASE, 0);
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}
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/*
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* A small note about bridges and interrupts. The DECchip 21050 (and
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* later) adheres to the PCI-PCI bridge specification. This says that
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* the interrupts on the other side of a bridge are swizzled in the
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* following manner:
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*
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* Dev Interrupt Interrupt
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* Pin on Pin on
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* Device Connector
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*
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* 4 A A
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* B B
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* C C
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* D D
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*
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* 5 A B
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* B C
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* C D
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* D A
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*
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* 6 A C
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* B D
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* C A
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* D B
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*
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* 7 A D
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* B A
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* C B
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* D C
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*
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* Where A = pin 1, B = pin 2 and so on and pin=0 = default = A.
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* Thus, each swizzle is ((pin-1) + (device#-4)) % 4
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*/
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/*
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* This routine handles multiple bridges.
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*/
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static u8 __init integrator_swizzle(struct pci_dev *dev, u8 *pinp)
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{
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if (*pinp == 0)
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*pinp = 1;
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return pci_common_swizzle(dev, pinp);
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}
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static int irq_tab[4] __initdata = {
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IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3
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};
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/*
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* map the specified device/slot/pin to an IRQ. This works out such
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* that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1.
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*/
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static int __init integrator_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int intnr = ((slot - 9) + (pin - 1)) & 3;
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return irq_tab[intnr];
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}
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static struct hw_pci integrator_pci __initdata = {
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.swizzle = integrator_swizzle,
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.map_irq = integrator_map_irq,
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.setup = pci_v3_setup,
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.nr_controllers = 1,
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.ops = &pci_v3_ops,
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.preinit = pci_v3_preinit,
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.postinit = pci_v3_postinit,
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};
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static int __init integrator_pci_init(void)
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{
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if (machine_is_integrator())
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pci_common_init(&integrator_pci);
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return 0;
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}
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subsys_initcall(integrator_pci_init);
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