forked from luck/tmp_suning_uos_patched
pinctrl: sunxi: fix V3s pinctrl driver IRQ bank base
The V3s pin controller doesn't have the bank 0 (starts at address
0x200), which is like A33. However, this is not worked around when
developing the driver, which makes IRQ not working.
Fix the IRQ bank base.
Fixes: 56d9e4a760
("pinctrl: sunxi: add driver for V3s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -297,6 +297,7 @@ static const struct sunxi_pinctrl_desc sun8i_v3s_pinctrl_data = {
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.pins = sun8i_v3s_pins,
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.npins = ARRAY_SIZE(sun8i_v3s_pins),
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.irq_banks = 2,
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.irq_bank_base = 1,
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.irq_read_needs_mux = true
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};
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