forked from luck/tmp_suning_uos_patched
spi/bfin_spi: utilize the SPI interrupt in PIO mode
The current behavior in PIO mode is to poll the SPI status registers which can obviously lead to higher latencies when doing a lot of SPI traffic. There is a SPI interrupt which can be used instead to signal individual completion of transactions. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Yi Li
Mike Frysinger
parent
bb8beecd98
commit
f6a6d96685
@ -92,6 +92,9 @@ struct driver_data {
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dma_addr_t rx_dma;
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dma_addr_t tx_dma;
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int irq_requested;
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int spi_irq;
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size_t rx_map_len;
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size_t tx_map_len;
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u8 n_bytes;
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@ -115,6 +118,7 @@ struct chip_data {
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u16 cs_chg_udelay; /* Some devices require > 255usec delay */
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u32 cs_gpio;
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u16 idle_tx_val;
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u8 pio_interrupt; /* use spi data irq */
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void (*write) (struct driver_data *);
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void (*read) (struct driver_data *);
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void (*duplex) (struct driver_data *);
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@ -525,6 +529,79 @@ static void bfin_spi_giveback(struct driver_data *drv_data)
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msg->complete(msg->context);
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}
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/* spi data irq handler */
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static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
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{
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struct driver_data *drv_data = dev_id;
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struct chip_data *chip = drv_data->cur_chip;
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struct spi_message *msg = drv_data->cur_msg;
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int n_bytes = drv_data->n_bytes;
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/* wait until transfer finished. */
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while (!(read_STAT(drv_data) & BIT_STAT_RXS))
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cpu_relax();
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if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
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(drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
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/* last read */
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if (drv_data->rx) {
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dev_dbg(&drv_data->pdev->dev, "last read\n");
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if (n_bytes == 2)
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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else if (n_bytes == 1)
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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drv_data->rx += n_bytes;
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}
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msg->actual_length += drv_data->len_in_bytes;
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if (drv_data->cs_change)
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bfin_spi_cs_deactive(drv_data, chip);
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/* Move to next transfer */
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msg->state = bfin_spi_next_transfer(drv_data);
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disable_irq(drv_data->spi_irq);
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/* Schedule transfer tasklet */
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tasklet_schedule(&drv_data->pump_transfers);
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return IRQ_HANDLED;
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}
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if (drv_data->rx && drv_data->tx) {
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/* duplex */
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dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
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if (drv_data->n_bytes == 2) {
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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} else if (drv_data->n_bytes == 1) {
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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}
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} else if (drv_data->rx) {
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/* read */
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dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
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if (drv_data->n_bytes == 2)
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*(u16 *) (drv_data->rx) = read_RDBR(drv_data);
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else if (drv_data->n_bytes == 1)
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*(u8 *) (drv_data->rx) = read_RDBR(drv_data);
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write_TDBR(drv_data, chip->idle_tx_val);
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} else if (drv_data->tx) {
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/* write */
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dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
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bfin_spi_dummy_read(drv_data);
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if (drv_data->n_bytes == 2)
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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else if (drv_data->n_bytes == 1)
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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}
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if (drv_data->tx)
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drv_data->tx += n_bytes;
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if (drv_data->rx)
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drv_data->rx += n_bytes;
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return IRQ_HANDLED;
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}
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static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
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{
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struct driver_data *drv_data = dev_id;
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@ -700,6 +777,7 @@ static void bfin_spi_pump_transfers(unsigned long data)
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default:
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/* No change, the same as default setting */
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transfer->bits_per_word = chip->bits_per_word;
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drv_data->n_bytes = chip->n_bytes;
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width = chip->width;
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drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer;
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@ -842,60 +920,86 @@ static void bfin_spi_pump_transfers(unsigned long data)
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dma_enable_irq(drv_data->dma_channel);
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local_irq_restore(flags);
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} else {
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/* IO mode write then read */
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dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
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return;
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}
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/* we always use SPI_WRITE mode. SPI_READ mode
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seems to have problems with setting up the
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output value in TDBR prior to the transfer. */
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if (chip->pio_interrupt) {
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/* use write mode. spi irq should have been disabled */
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cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
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write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
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if (full_duplex) {
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/* full duplex mode */
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BUG_ON((drv_data->tx_end - drv_data->tx) !=
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(drv_data->rx_end - drv_data->rx));
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dev_dbg(&drv_data->pdev->dev,
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"IO duplex: cr is 0x%x\n", cr);
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/* discard old RX data and clear RXS */
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bfin_spi_dummy_read(drv_data);
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drv_data->duplex(drv_data);
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if (drv_data->tx != drv_data->tx_end)
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tranf_success = 0;
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} else if (drv_data->tx != NULL) {
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/* write only half duplex */
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dev_dbg(&drv_data->pdev->dev,
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"IO write: cr is 0x%x\n", cr);
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drv_data->write(drv_data);
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if (drv_data->tx != drv_data->tx_end)
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tranf_success = 0;
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} else if (drv_data->rx != NULL) {
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/* read only half duplex */
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dev_dbg(&drv_data->pdev->dev,
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"IO read: cr is 0x%x\n", cr);
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drv_data->read(drv_data);
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if (drv_data->rx != drv_data->rx_end)
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tranf_success = 0;
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/* start transfer */
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if (drv_data->tx == NULL)
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write_TDBR(drv_data, chip->idle_tx_val);
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else {
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if (transfer->bits_per_word == 8)
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write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
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else if (transfer->bits_per_word == 16)
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write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
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drv_data->tx += drv_data->n_bytes;
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}
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if (!tranf_success) {
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dev_dbg(&drv_data->pdev->dev,
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"IO write error!\n");
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message->state = ERROR_STATE;
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} else {
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/* Update total byte transfered */
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message->actual_length += drv_data->len_in_bytes;
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/* Move to next transfer of this msg */
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message->state = bfin_spi_next_transfer(drv_data);
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if (drv_data->cs_change)
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bfin_spi_cs_deactive(drv_data, chip);
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}
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/* Schedule next transfer tasklet */
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tasklet_schedule(&drv_data->pump_transfers);
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/* once TDBR is empty, interrupt is triggered */
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enable_irq(drv_data->spi_irq);
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return;
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}
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/* IO mode */
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dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
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/* we always use SPI_WRITE mode. SPI_READ mode
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seems to have problems with setting up the
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output value in TDBR prior to the transfer. */
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write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
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if (full_duplex) {
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/* full duplex mode */
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BUG_ON((drv_data->tx_end - drv_data->tx) !=
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(drv_data->rx_end - drv_data->rx));
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dev_dbg(&drv_data->pdev->dev,
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"IO duplex: cr is 0x%x\n", cr);
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drv_data->duplex(drv_data);
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if (drv_data->tx != drv_data->tx_end)
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tranf_success = 0;
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} else if (drv_data->tx != NULL) {
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/* write only half duplex */
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dev_dbg(&drv_data->pdev->dev,
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"IO write: cr is 0x%x\n", cr);
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drv_data->write(drv_data);
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if (drv_data->tx != drv_data->tx_end)
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tranf_success = 0;
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} else if (drv_data->rx != NULL) {
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/* read only half duplex */
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dev_dbg(&drv_data->pdev->dev,
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"IO read: cr is 0x%x\n", cr);
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drv_data->read(drv_data);
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if (drv_data->rx != drv_data->rx_end)
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tranf_success = 0;
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}
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if (!tranf_success) {
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dev_dbg(&drv_data->pdev->dev,
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"IO write error!\n");
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message->state = ERROR_STATE;
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} else {
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/* Update total byte transfered */
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message->actual_length += drv_data->len_in_bytes;
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/* Move to next transfer of this msg */
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message->state = bfin_spi_next_transfer(drv_data);
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if (drv_data->cs_change)
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bfin_spi_cs_deactive(drv_data, chip);
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}
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/* Schedule next transfer tasklet */
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tasklet_schedule(&drv_data->pump_transfers);
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}
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/* pop a msg from queue and kick off real transfer */
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@ -1047,6 +1151,7 @@ static int bfin_spi_setup(struct spi_device *spi)
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chip->cs_chg_udelay = chip_info->cs_chg_udelay;
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chip->cs_gpio = chip_info->cs_gpio;
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chip->idle_tx_val = chip_info->idle_tx_val;
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chip->pio_interrupt = chip_info->pio_interrupt;
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}
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/* translate common spi framework into our register */
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@ -1096,6 +1201,11 @@ static int bfin_spi_setup(struct spi_device *spi)
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goto error;
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}
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if (chip->enable_dma && chip->pio_interrupt) {
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dev_err(&spi->dev, "enable_dma is set, "
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"do not set pio_interrupt\n");
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goto error;
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}
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/*
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* if any one SPI chip is registered and wants DMA, request the
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* DMA channel for it
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@ -1119,6 +1229,18 @@ static int bfin_spi_setup(struct spi_device *spi)
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dma_disable_irq(drv_data->dma_channel);
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}
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if (chip->pio_interrupt && !drv_data->irq_requested) {
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ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
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IRQF_DISABLED, "BFIN_SPI", drv_data);
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if (ret) {
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dev_err(&spi->dev, "Unable to register spi IRQ\n");
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goto error;
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}
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drv_data->irq_requested = 1;
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/* we use write mode, spi irq has to be disabled here */
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disable_irq(drv_data->spi_irq);
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}
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if (chip->chip_select_num == 0) {
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ret = gpio_request(chip->cs_gpio, spi->modalias);
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if (ret) {
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@ -1328,11 +1450,19 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
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goto out_error_ioremap;
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}
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drv_data->dma_channel = platform_get_irq(pdev, 0);
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if (drv_data->dma_channel < 0) {
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res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
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if (res == NULL) {
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dev_err(dev, "No DMA channel specified\n");
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status = -ENOENT;
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goto out_error_no_dma_ch;
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goto out_error_free_io;
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}
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drv_data->dma_channel = res->start;
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drv_data->spi_irq = platform_get_irq(pdev, 0);
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if (drv_data->spi_irq < 0) {
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dev_err(dev, "No spi pio irq specified\n");
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status = -ENOENT;
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goto out_error_free_io;
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}
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/* Initial and start queue */
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@ -1375,7 +1505,7 @@ static int __init bfin_spi_probe(struct platform_device *pdev)
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out_error_queue_alloc:
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bfin_spi_destroy_queue(drv_data);
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out_error_no_dma_ch:
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out_error_free_io:
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iounmap((void *) drv_data->regs_base);
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out_error_ioremap:
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out_error_get_res:
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@ -1407,6 +1537,11 @@ static int __devexit bfin_spi_remove(struct platform_device *pdev)
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free_dma(drv_data->dma_channel);
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}
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if (drv_data->irq_requested) {
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free_irq(drv_data->spi_irq, drv_data);
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drv_data->irq_requested = 0;
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}
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/* Disconnect from the SPI framework */
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spi_unregister_master(drv_data->master);
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