forked from luck/tmp_suning_uos_patched
ARM: tegra: Tegra30 speedo-based process identification
This patch adds speedo-based process identification support for Tegra30. Signed-off-by: Danny Huang <dahuang@nvidia.com> [swarren s/Tegra3/Tegra30/ in log print, s/T30/Tegra30/ in commit description] Signed-off-by: Stephen Warren <swarren@nvidia.com>
This commit is contained in:
Danny Huang
Stephen Warren
parent
25cd5a3914
commit
f8ddda713b
@ -17,6 +17,7 @@ obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
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obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o
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obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o
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obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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obj-$(CONFIG_SMP) += reset.o
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@ -30,11 +30,13 @@
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#define FUSE_SKU_INFO 0x110
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#define TEGRA20_FUSE_SPARE_BIT 0x200
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#define TEGRA30_FUSE_SPARE_BIT 0x244
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int tegra_sku_id;
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int tegra_cpu_process_id;
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int tegra_core_process_id;
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int tegra_chip_id;
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int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
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int tegra_soc_speedo_id;
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enum tegra_revision tegra_revision;
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@ -120,13 +122,18 @@ void tegra_init_fuse(void)
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id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
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tegra_chip_id = (id >> 8) & 0xff;
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tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
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switch (tegra_chip_id) {
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case TEGRA20:
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tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
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tegra_init_speedo_data = &tegra20_init_speedo_data;
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break;
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case TEGRA30:
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tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT;
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tegra_init_speedo_data = &tegra30_init_speedo_data;
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break;
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default:
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pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id);
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tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT;
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tegra_init_speedo_data = &tegra_get_process_id;
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}
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@ -42,6 +42,7 @@ extern int tegra_sku_id;
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extern int tegra_cpu_process_id;
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extern int tegra_core_process_id;
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extern int tegra_chip_id;
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extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */
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extern int tegra_soc_speedo_id;
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extern enum tegra_revision tegra_revision;
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@ -58,4 +59,10 @@ void tegra20_init_speedo_data(void);
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static inline void tegra20_init_speedo_data(void) {}
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#endif
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#ifdef CONFIG_ARCH_TEGRA_3x_SOC
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void tegra30_init_speedo_data(void);
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#else
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static inline void tegra30_init_speedo_data(void) {}
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#endif
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#endif
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292
arch/arm/mach-tegra/tegra30_speedo.c
Normal file
292
arch/arm/mach-tegra/tegra30_speedo.c
Normal file
@ -0,0 +1,292 @@
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/*
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* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/kernel.h>
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#include <linux/bug.h>
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#include "fuse.h"
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#define CORE_PROCESS_CORNERS_NUM 1
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#define CPU_PROCESS_CORNERS_NUM 6
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#define FUSE_SPEEDO_CALIB_0 0x114
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#define FUSE_PACKAGE_INFO 0X1FC
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#define FUSE_TEST_PROG_VER 0X128
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#define G_SPEEDO_BIT_MINUS1 58
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#define G_SPEEDO_BIT_MINUS1_R 59
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#define G_SPEEDO_BIT_MINUS2 60
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#define G_SPEEDO_BIT_MINUS2_R 61
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#define LP_SPEEDO_BIT_MINUS1 62
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#define LP_SPEEDO_BIT_MINUS1_R 63
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#define LP_SPEEDO_BIT_MINUS2 64
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#define LP_SPEEDO_BIT_MINUS2_R 65
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enum {
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THRESHOLD_INDEX_0,
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THRESHOLD_INDEX_1,
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THRESHOLD_INDEX_2,
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THRESHOLD_INDEX_3,
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THRESHOLD_INDEX_4,
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THRESHOLD_INDEX_5,
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THRESHOLD_INDEX_6,
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THRESHOLD_INDEX_7,
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THRESHOLD_INDEX_8,
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THRESHOLD_INDEX_9,
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THRESHOLD_INDEX_10,
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THRESHOLD_INDEX_11,
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THRESHOLD_INDEX_COUNT,
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};
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static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
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{180},
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{170},
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{195},
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{180},
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{168},
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{192},
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{180},
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{170},
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{195},
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{180},
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{180},
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{180},
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};
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static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
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{306, 338, 360, 376, UINT_MAX},
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{295, 336, 358, 375, UINT_MAX},
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{325, 325, 358, 375, UINT_MAX},
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{325, 325, 358, 375, UINT_MAX},
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{292, 324, 348, 364, UINT_MAX},
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{324, 324, 348, 364, UINT_MAX},
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{324, 324, 348, 364, UINT_MAX},
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{295, 336, 358, 375, UINT_MAX},
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{358, 358, 358, 358, 397, UINT_MAX},
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{364, 364, 364, 364, 397, UINT_MAX},
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{295, 336, 358, 375, 391, UINT_MAX},
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{295, 336, 358, 375, 391, UINT_MAX},
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};
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static int threshold_index;
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static int package_id;
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static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp)
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{
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u32 reg;
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int ate_ver;
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int bit_minus1;
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int bit_minus2;
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reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0);
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*speedo_lp = (reg & 0xFFFF) * 4;
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*speedo_g = ((reg >> 16) & 0xFFFF) * 4;
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ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER);
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pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10);
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if (ate_ver >= 26) {
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bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1);
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bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R);
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bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2);
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bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R);
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*speedo_lp |= (bit_minus1 << 1) | bit_minus2;
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bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1);
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bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R);
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bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2);
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bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R);
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*speedo_g |= (bit_minus1 << 1) | bit_minus2;
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} else {
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*speedo_lp |= 0x3;
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*speedo_g |= 0x3;
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}
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}
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static void rev_sku_to_speedo_ids(int rev, int sku)
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{
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switch (rev) {
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case TEGRA_REVISION_A01:
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tegra_cpu_speedo_id = 0;
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tegra_soc_speedo_id = 0;
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threshold_index = THRESHOLD_INDEX_0;
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break;
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case TEGRA_REVISION_A02:
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case TEGRA_REVISION_A03:
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switch (sku) {
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case 0x87:
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case 0x82:
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tegra_cpu_speedo_id = 1;
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tegra_soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_1;
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break;
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case 0x81:
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switch (package_id) {
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case 1:
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tegra_cpu_speedo_id = 2;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_2;
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break;
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case 2:
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tegra_cpu_speedo_id = 4;
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tegra_soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_7;
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break;
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default:
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pr_err("Tegra30: Unknown pkg %d\n", package_id);
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BUG();
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break;
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}
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break;
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case 0x80:
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switch (package_id) {
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case 1:
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tegra_cpu_speedo_id = 5;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_8;
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break;
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case 2:
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tegra_cpu_speedo_id = 6;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_9;
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break;
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default:
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pr_err("Tegra30: Unknown pkg %d\n", package_id);
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BUG();
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break;
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}
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break;
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case 0x83:
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switch (package_id) {
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case 1:
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tegra_cpu_speedo_id = 7;
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tegra_soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_10;
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break;
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case 2:
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tegra_cpu_speedo_id = 3;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_3;
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break;
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default:
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pr_err("Tegra30: Unknown pkg %d\n", package_id);
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BUG();
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break;
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}
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break;
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case 0x8F:
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tegra_cpu_speedo_id = 8;
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tegra_soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_11;
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break;
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case 0x08:
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tegra_cpu_speedo_id = 1;
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tegra_soc_speedo_id = 1;
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threshold_index = THRESHOLD_INDEX_4;
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break;
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case 0x02:
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tegra_cpu_speedo_id = 2;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_5;
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break;
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case 0x04:
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tegra_cpu_speedo_id = 3;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_6;
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break;
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case 0:
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switch (package_id) {
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case 1:
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tegra_cpu_speedo_id = 2;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_2;
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break;
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case 2:
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tegra_cpu_speedo_id = 3;
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tegra_soc_speedo_id = 2;
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threshold_index = THRESHOLD_INDEX_3;
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break;
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default:
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pr_err("Tegra30: Unknown pkg %d\n", package_id);
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BUG();
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break;
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}
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break;
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default:
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pr_warn("Tegra30: Unknown SKU %d\n", sku);
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tegra_cpu_speedo_id = 0;
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tegra_soc_speedo_id = 0;
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threshold_index = THRESHOLD_INDEX_0;
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break;
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}
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break;
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default:
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pr_warn("Tegra30: Unknown chip rev %d\n", rev);
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tegra_cpu_speedo_id = 0;
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tegra_soc_speedo_id = 0;
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threshold_index = THRESHOLD_INDEX_0;
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break;
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}
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}
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void tegra30_init_speedo_data(void)
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{
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u32 cpu_speedo_val;
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u32 core_speedo_val;
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int i;
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BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
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THRESHOLD_INDEX_COUNT);
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package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F;
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rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id);
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fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val);
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pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val);
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pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val);
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for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) {
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if (cpu_speedo_val < cpu_process_speedos[threshold_index][i])
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break;
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}
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tegra_cpu_process_id = i - 1;
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if (tegra_cpu_process_id == -1) {
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pr_warn("Tegra30: CPU speedo value %3d out of range",
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cpu_speedo_val);
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tegra_cpu_process_id = 0;
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tegra_cpu_speedo_id = 1;
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}
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for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) {
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if (core_speedo_val < core_process_speedos[threshold_index][i])
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break;
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}
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tegra_core_process_id = i - 1;
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if (tegra_core_process_id == -1) {
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pr_warn("Tegra30: CORE speedo value %3d out of range",
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core_speedo_val);
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tegra_core_process_id = 0;
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tegra_soc_speedo_id = 1;
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}
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pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d",
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tegra_cpu_speedo_id, tegra_soc_speedo_id);
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}
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