forked from luck/tmp_suning_uos_patched
ARM: OMAP1: Update dpll1 default rate reprogramming method
According to comments in omap1_select_table_rate(), reprogramming dpll1 is tricky, and should always be done from SRAM. While being at it, move OMAP730 special case handling inside omap_sram_reprogram_clock(). Created on top of version 2 of the series "ARM: OMAP1: Fix dpll1 reprogramming related issues", which it depends on. Tested on Amstrad Delta. Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -218,12 +218,8 @@ int omap1_select_table_rate(struct clk *clk, unsigned long rate)
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/*
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* In most cases we should not need to reprogram DPLL.
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* Reprogramming the DPLL is tricky, it must be done from SRAM.
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* (on 730, bit 13 must always be 1)
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*/
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if (cpu_is_omap7xx())
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val | 0x2000);
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else
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
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omap_sram_reprogram_clock(ptr->dpllctl_val, ptr->ckctl_val);
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/* XXX Do we need to recalculate the tree below DPLL1 at this point? */
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ck_dpll1_p->rate = ptr->pll_rate;
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@ -25,6 +25,7 @@
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#include <plat/clock.h>
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#include <plat/cpu.h>
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#include <plat/clkdev_omap.h>
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#include <plat/sram.h> /* for omap_sram_reprogram_clock() */
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#include <plat/usb.h> /* for OTG_BASE */
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#include "clock.h"
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@ -944,8 +945,10 @@ void __init omap1_clk_late_init(void)
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/* Find the highest supported frequency and enable it */
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if (omap1_select_table_rate(&virtual_ck_mpu, ~0)) {
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pr_err("System frequencies not set, using default. Check your config.\n");
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omap_writew(0x2290, DPLL_CTL);
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omap_writew(cpu_is_omap7xx() ? 0x2005 : 0x0005, ARM_CKCTL);
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/*
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* Reprogramming the DPLL is tricky, it must be done from SRAM.
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*/
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omap_sram_reprogram_clock(0x2290, 0x0005);
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ck_dpll1.rate = OMAP1_DPLL1_SANE_VALUE;
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}
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propagate_rate(&ck_dpll1);
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@ -222,6 +222,9 @@ static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
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void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
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{
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BUG_ON(!_omap_sram_reprogram_clock);
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/* On 730, bit 13 must always be 1 */
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if (cpu_is_omap7xx())
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ckctl |= 0x2000;
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_omap_sram_reprogram_clock(dpllctl, ckctl);
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}
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