forked from luck/tmp_suning_uos_patched
spi: tegra114: add support for interrupt mask
This patch creates tegra_spi_soc_data structure to maintain and implement SPI HW feature differences between different Tegra chips and also creates a separate compatible string for T124/T210. Tegra210 and later has a separate interrupt mask register SPI_INTR_MASK for enabling or disabling interrupts while Tegra124 and prior uses interrupt enable bits in SPI_DMA_CTL register. This patch creates flag has_intr_mask_reg in tegra_spi_soc_data to identify this and implements accordingly. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Mark Brown <broonie@kernel.org>
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9d199231b0
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@ -149,6 +149,8 @@
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#define SPI_TX_FIFO 0x108
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#define SPI_RX_FIFO 0x188
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#define SPI_INTR_MASK 0x18c
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#define SPI_INTR_ALL_MASK (0x1fUL << 25)
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#define MAX_CHIP_SELECT 4
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#define SPI_FIFO_DEPTH 64
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#define DATA_DIR_TX (1 << 0)
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@ -161,6 +163,10 @@
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#define MAX_HOLD_CYCLES 16
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#define SPI_DEFAULT_SPEED 25000000
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struct tegra_spi_soc_data {
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bool has_intr_mask_reg;
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};
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struct tegra_spi_data {
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struct device *dev;
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struct spi_master *master;
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@ -211,6 +217,7 @@ struct tegra_spi_data {
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u32 *tx_dma_buf;
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dma_addr_t tx_dma_phys;
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struct dma_async_tx_descriptor *tx_dma_desc;
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const struct tegra_spi_soc_data *soc_data;
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};
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static int tegra_spi_runtime_suspend(struct device *dev);
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@ -554,11 +561,13 @@ static int tegra_spi_start_dma_based_transfer(
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dma_burst = 8;
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}
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if (tspi->cur_direction & DATA_DIR_TX)
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val |= SPI_IE_TX;
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if (!tspi->soc_data->has_intr_mask_reg) {
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if (tspi->cur_direction & DATA_DIR_TX)
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val |= SPI_IE_TX;
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if (tspi->cur_direction & DATA_DIR_RX)
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val |= SPI_IE_RX;
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if (tspi->cur_direction & DATA_DIR_RX)
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val |= SPI_IE_RX;
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}
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tegra_spi_writel(tspi, val, SPI_DMA_CTL);
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tspi->dma_control_reg = val;
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@ -847,6 +856,12 @@ static int tegra_spi_setup(struct spi_device *spi)
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return ret;
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}
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if (tspi->soc_data->has_intr_mask_reg) {
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val = tegra_spi_readl(tspi, SPI_INTR_MASK);
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val &= ~SPI_INTR_ALL_MASK;
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tegra_spi_writel(tspi, val, SPI_INTR_MASK);
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}
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spin_lock_irqsave(&tspi->lock, flags);
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val = tspi->def_command1_reg;
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if (spi->mode & SPI_CS_HIGH)
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@ -1135,8 +1150,29 @@ static irqreturn_t tegra_spi_isr(int irq, void *context_data)
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return IRQ_WAKE_THREAD;
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}
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static struct tegra_spi_soc_data tegra114_spi_soc_data = {
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.has_intr_mask_reg = false,
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};
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static struct tegra_spi_soc_data tegra124_spi_soc_data = {
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.has_intr_mask_reg = false,
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};
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static struct tegra_spi_soc_data tegra210_spi_soc_data = {
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.has_intr_mask_reg = true,
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};
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static const struct of_device_id tegra_spi_of_match[] = {
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{ .compatible = "nvidia,tegra114-spi", },
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{
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.compatible = "nvidia,tegra114-spi",
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.data = &tegra114_spi_soc_data,
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}, {
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.compatible = "nvidia,tegra124-spi",
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.data = &tegra124_spi_soc_data,
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}, {
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.compatible = "nvidia,tegra210-spi",
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.data = &tegra210_spi_soc_data,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
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@ -1177,6 +1213,13 @@ static int tegra_spi_probe(struct platform_device *pdev)
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tspi->dev = &pdev->dev;
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spin_lock_init(&tspi->lock);
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tspi->soc_data = of_device_get_match_data(&pdev->dev);
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if (!tspi->soc_data) {
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dev_err(&pdev->dev, "unsupported tegra\n");
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ret = -ENODEV;
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goto exit_free_master;
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}
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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tspi->base = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(tspi->base)) {
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