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e1000e: 82577/82578 requires a different method to configure LPLU

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Unlike previous ICHx-based parts, the PCH-based parts (82577/82578) require
LPLU (Low Power Link Up, or "reverse auto-negotiation") to be configured in
the PHY rather than the MAC.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Bruce Allan 2009-10-26 11:23:25 +00:00 committed by David S. Miller
parent 53ac5a8875
commit fa2ce13ca7
1 changed files with 40 additions and 0 deletions
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40
drivers/net/e1000e/ich8lan.c
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@ -124,6 +124,11 @@
#define SW_FLAG_TIMEOUT 1000 /* SW Semaphore flag timeout in milliseconds */
/* OEM Bits Phy Register */
#define HV_OEM_BITS PHY_REG(768, 25)
#define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */
#define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */
/* ICH GbE Flash Hardware Sequencing Flash Status Register bit breakdown */
/* Offset 04h HSFSTS */
union ich8_hws_flash_status {
@ -202,6 +207,7 @@ static s32 e1000_setup_led_pchlan(struct e1000_hw *hw);
static s32 e1000_cleanup_led_pchlan(struct e1000_hw *hw);
static s32 e1000_led_on_pchlan(struct e1000_hw *hw);
static s32 e1000_led_off_pchlan(struct e1000_hw *hw);
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active);
static inline u16 __er16flash(struct e1000_hw *hw, unsigned long reg)
{
@ -244,6 +250,8 @@ static s32 e1000_init_phy_params_pchlan(struct e1000_hw *hw)
phy->ops.check_polarity = e1000_check_polarity_ife_ich8lan;
phy->ops.read_phy_reg = e1000_read_phy_reg_hv;
phy->ops.set_d0_lplu_state = e1000_set_lplu_state_pchlan;
phy->ops.set_d3_lplu_state = e1000_set_lplu_state_pchlan;
phy->ops.write_phy_reg = e1000_write_phy_reg_hv;
phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
@ -1059,6 +1067,38 @@ static s32 e1000_check_polarity_ife_ich8lan(struct e1000_hw *hw)
return ret_val;
}
/**
* e1000_set_lplu_state_pchlan - Set Low Power Link Up state
* @hw: pointer to the HW structure
* @active: true to enable LPLU, false to disable
*
* Sets the LPLU state according to the active flag. For PCH, if OEM write
* bit are disabled in the NVM, writing the LPLU bits in the MAC will not set
* the phy speed. This function will manually set the LPLU bit and restart
* auto-neg as hw would do. D3 and D0 LPLU will call the same function
* since it configures the same bit.
**/
static s32 e1000_set_lplu_state_pchlan(struct e1000_hw *hw, bool active)
{
s32 ret_val = 0;
u16 oem_reg;
ret_val = e1e_rphy(hw, HV_OEM_BITS, &oem_reg);
if (ret_val)
goto out;
if (active)
oem_reg |= HV_OEM_BITS_LPLU;
else
oem_reg &= ~HV_OEM_BITS_LPLU;
oem_reg |= HV_OEM_BITS_RESTART_AN;
ret_val = e1e_wphy(hw, HV_OEM_BITS, oem_reg);
out:
return ret_val;
}
/**
* e1000_set_d0_lplu_state_ich8lan - Set Low Power Linkup D0 state
* @hw: pointer to the HW structure