forked from luck/tmp_suning_uos_patched
Merge remote-tracking branches 'spi/topic/spidev', 'spi/topic/sunxi', 'spi/topic/ti-qspi', 'spi/topic/topcliff-pch' and 'spi/topic/xlp' into spi-next
This commit is contained in:
Mark Brown
commit
fafd679407
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@ -1,7 +1,7 @@
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Allwinner A31 SPI controller
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Allwinner A31/H3 SPI controller
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Required properties:
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- compatible: Should be "allwinner,sun6i-a31-spi".
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- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
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- reg: Should contain register location and length.
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- interrupts: Should contain interrupt.
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- clocks: phandle to the clocks feeding the SPI controller. Two are
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@ -12,6 +12,11 @@ Required properties:
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- resets: phandle to the reset controller asserting this device in
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reset
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Optional properties:
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- dmas: DMA specifiers for rx and tx dma. See the DMA client binding,
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Documentation/devicetree/bindings/dma/dma.txt
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- dma-names: DMA request names should include "rx" and "tx" if present.
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Example:
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spi1: spi@01c69000 {
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@ -22,3 +27,19 @@ spi1: spi@01c69000 {
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clock-names = "ahb", "mod";
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resets = <&ahb1_rst 21>;
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};
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spi0: spi@01c68000 {
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compatible = "allwinner,sun8i-h3-spi";
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reg = <0x01c68000 0x1000>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
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clock-names = "ahb", "mod";
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dmas = <&dma 23>, <&dma 23>;
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dma-names = "rx", "tx";
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pinctrl-names = "default";
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pinctrl-0 = <&spi0_pins>;
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resets = <&ccu RST_BUS_SPI0>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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@ -46,6 +46,8 @@
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#define SUN4I_CTL_TP BIT(18)
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#define SUN4I_INT_CTL_REG 0x0c
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#define SUN4I_INT_CTL_RF_F34 BIT(4)
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#define SUN4I_INT_CTL_TF_E34 BIT(12)
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#define SUN4I_INT_CTL_TC BIT(16)
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#define SUN4I_INT_STA_REG 0x10
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@ -61,11 +63,14 @@
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN4I_CLK_CTL_DRS BIT(12)
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#define SUN4I_MAX_XFER_SIZE 0xffffff
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#define SUN4I_BURST_CNT_REG 0x20
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#define SUN4I_BURST_CNT(cnt) ((cnt) & 0xffffff)
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#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_XMIT_CNT_REG 0x24
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & 0xffffff)
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_FIFO_STA_REG 0x28
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#define SUN4I_FIFO_STA_RF_CNT_MASK 0x7f
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@ -96,6 +101,31 @@ static inline void sun4i_spi_write(struct sun4i_spi *sspi, u32 reg, u32 value)
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writel(value, sspi->base_addr + reg);
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}
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static inline u32 sun4i_spi_get_tx_fifo_count(struct sun4i_spi *sspi)
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{
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u32 reg = sun4i_spi_read(sspi, SUN4I_FIFO_STA_REG);
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reg >>= SUN4I_FIFO_STA_TF_CNT_BITS;
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return reg & SUN4I_FIFO_STA_TF_CNT_MASK;
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}
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static inline void sun4i_spi_enable_interrupt(struct sun4i_spi *sspi, u32 mask)
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{
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u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
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reg |= mask;
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
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}
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static inline void sun4i_spi_disable_interrupt(struct sun4i_spi *sspi, u32 mask)
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{
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u32 reg = sun4i_spi_read(sspi, SUN4I_INT_CTL_REG);
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reg &= ~mask;
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, reg);
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}
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static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
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{
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u32 reg, cnt;
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@ -118,10 +148,13 @@ static inline void sun4i_spi_drain_fifo(struct sun4i_spi *sspi, int len)
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static inline void sun4i_spi_fill_fifo(struct sun4i_spi *sspi, int len)
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{
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u32 cnt;
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u8 byte;
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if (len > sspi->len)
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len = sspi->len;
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/* See how much data we can fit */
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cnt = SUN4I_FIFO_DEPTH - sun4i_spi_get_tx_fifo_count(sspi);
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len = min3(len, (int)cnt, sspi->len);
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while (len--) {
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byte = sspi->tx_buf ? *sspi->tx_buf++ : 0;
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@ -184,10 +217,10 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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u32 reg;
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN4I_FIFO_DEPTH)
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if (tfr->len > SUN4I_MAX_XFER_SIZE)
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return -EMSGSIZE;
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if (tfr->tx_buf && tfr->len >= SUN4I_FIFO_DEPTH)
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if (tfr->tx_buf && tfr->len >= SUN4I_MAX_XFER_SIZE)
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return -EMSGSIZE;
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reinit_completion(&sspi->done);
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@ -286,7 +319,11 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH - 1);
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/* Enable the interrupts */
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, SUN4I_INT_CTL_TC);
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sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TC |
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SUN4I_INT_CTL_RF_F34);
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/* Only enable Tx FIFO interrupt if we really need it */
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if (tx_len > SUN4I_FIFO_DEPTH)
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sun4i_spi_enable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
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/* Start the transfer */
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reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
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@ -306,7 +343,6 @@ static int sun4i_spi_transfer_one(struct spi_master *master,
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goto out;
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}
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sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
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out:
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sun4i_spi_write(sspi, SUN4I_INT_CTL_REG, 0);
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@ -322,10 +358,33 @@ static irqreturn_t sun4i_spi_handler(int irq, void *dev_id)
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/* Transfer complete */
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if (status & SUN4I_INT_CTL_TC) {
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TC);
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sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
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complete(&sspi->done);
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return IRQ_HANDLED;
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}
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/* Receive FIFO 3/4 full */
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if (status & SUN4I_INT_CTL_RF_F34) {
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sun4i_spi_drain_fifo(sspi, SUN4I_FIFO_DEPTH);
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/* Only clear the interrupt _after_ draining the FIFO */
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_RF_F34);
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return IRQ_HANDLED;
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}
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/* Transmit FIFO 3/4 empty */
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if (status & SUN4I_INT_CTL_TF_E34) {
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sun4i_spi_fill_fifo(sspi, SUN4I_FIFO_DEPTH);
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if (!sspi->len)
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/* nothing left to transmit */
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sun4i_spi_disable_interrupt(sspi, SUN4I_INT_CTL_TF_E34);
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/* Only clear the interrupt _after_ re-seeding the FIFO */
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sun4i_spi_write(sspi, SUN4I_INT_STA_REG, SUN4I_INT_CTL_TF_E34);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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@ -17,6 +17,7 @@
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/reset.h>
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@ -24,6 +25,7 @@
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#include <linux/spi/spi.h>
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#define SUN6I_FIFO_DEPTH 128
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#define SUN8I_FIFO_DEPTH 64
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#define SUN6I_GBL_CTL_REG 0x04
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#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
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@ -90,6 +92,7 @@ struct sun6i_spi {
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const u8 *tx_buf;
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u8 *rx_buf;
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int len;
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unsigned long fifo_depth;
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};
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static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
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@ -155,7 +158,9 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
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static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
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{
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return SUN6I_FIFO_DEPTH - 1;
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struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
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return sspi->fifo_depth - 1;
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}
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static int sun6i_spi_transfer_one(struct spi_master *master,
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@ -170,7 +175,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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u32 reg;
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/* We don't support transfer larger than the FIFO */
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if (tfr->len > SUN6I_FIFO_DEPTH)
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if (tfr->len > sspi->fifo_depth)
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return -EINVAL;
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reinit_completion(&sspi->done);
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@ -265,7 +270,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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SUN6I_BURST_CTL_CNT_STC(tx_len));
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/* Fill the TX FIFO */
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sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
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sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
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/* Enable the interrupts */
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
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@ -288,7 +293,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
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goto out;
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}
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sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
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sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
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out:
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sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
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@ -398,6 +403,8 @@ static int sun6i_spi_probe(struct platform_device *pdev)
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}
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sspi->master = master;
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sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
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master->max_speed_hz = 100 * 1000 * 1000;
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master->min_speed_hz = 3 * 1000;
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master->set_cs = sun6i_spi_set_cs;
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@ -470,7 +477,8 @@ static int sun6i_spi_remove(struct platform_device *pdev)
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}
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static const struct of_device_id sun6i_spi_match[] = {
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{ .compatible = "allwinner,sun6i-a31-spi", },
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{ .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
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{ .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
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{}
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};
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MODULE_DEVICE_TABLE(of, sun6i_spi_match);
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@ -411,6 +411,7 @@ static int ti_qspi_dma_xfer(struct ti_qspi *qspi, dma_addr_t dma_dst,
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tx->callback = ti_qspi_dma_callback;
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tx->callback_param = qspi;
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cookie = tx->tx_submit(tx);
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reinit_completion(&qspi->transfer_complete);
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ret = dma_submit_error(cookie);
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if (ret) {
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@ -1268,11 +1268,8 @@ static void pch_spi_free_resources(struct pch_spi_board_data *board_dat,
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static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
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struct pch_spi_data *data)
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{
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int retval = 0;
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dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__);
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/* reset PCH SPI h/w */
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pch_spi_reset(data->master);
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dev_dbg(&board_dat->pdev->dev,
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@ -1280,15 +1277,7 @@ static int pch_spi_get_resources(struct pch_spi_board_data *board_dat,
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dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__);
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if (retval != 0) {
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dev_err(&board_dat->pdev->dev,
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"%s FAIL:invoking pch_spi_free_resources\n", __func__);
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pch_spi_free_resources(board_dat, data);
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}
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dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval);
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return retval;
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return 0;
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}
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static void pch_free_dma_buf(struct pch_spi_board_data *board_dat,
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@ -451,6 +451,7 @@ static const struct of_device_id xlp_spi_dt_id[] = {
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{ .compatible = "netlogic,xlp832-spi" },
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{ },
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};
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MODULE_DEVICE_TABLE(of, xlp_spi_dt_id);
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static struct platform_driver xlp_spi_driver = {
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.probe = xlp_spi_probe,
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@ -696,6 +696,7 @@ static struct class *spidev_class;
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static const struct of_device_id spidev_dt_ids[] = {
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{ .compatible = "rohm,dh2228fv" },
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{ .compatible = "lineartechnology,ltc2488" },
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{ .compatible = "ge,achc" },
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{},
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};
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MODULE_DEVICE_TABLE(of, spidev_dt_ids);
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Block a user