forked from luck/tmp_suning_uos_patched
[ARM] pxa: introduce processor specific pxa27x_assert_ac97reset()
This is really pxa27x specific and should be kept in pxa27x.c. With this newly introduced function, the original set_resetgpio_mode() is deprecated. Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Cc: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
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@ -40,6 +40,25 @@ void pxa27x_clear_otgph(void)
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}
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EXPORT_SYMBOL(pxa27x_clear_otgph);
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static unsigned long ac97_reset_config[] = {
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GPIO95_AC97_nRESET,
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GPIO95_GPIO,
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GPIO113_AC97_nRESET,
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GPIO113_GPIO,
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};
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void pxa27x_assert_ac97reset(int reset_gpio, int on)
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{
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if (reset_gpio == 113)
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pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
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&ac97_reset_config[1], 1);
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if (reset_gpio == 95)
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pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
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&ac97_reset_config[3], 1);
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}
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EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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@ -32,6 +32,8 @@ static struct clk *ac97_clk;
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static struct clk *ac97conf_clk;
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static int reset_gpio;
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extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
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/*
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* Beware PXA27x bugs:
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*
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@ -42,45 +44,6 @@ static int reset_gpio;
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* 1 jiffy timeout if interrupt never comes).
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*/
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enum {
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RESETGPIO_FORCE_HIGH,
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RESETGPIO_FORCE_LOW,
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RESETGPIO_NORMAL_ALTFUNC
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};
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/**
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* set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
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* @mode: chosen action
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*
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* As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
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* must be done to insure proper work of AC97 reset line. This function
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* computes the correct gpio_mode for further use by reset functions, and
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* applied the change through pxa_gpio_mode.
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*/
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static void set_resetgpio_mode(int resetgpio_action)
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{
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int mode = 0;
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if (reset_gpio)
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switch (resetgpio_action) {
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case RESETGPIO_NORMAL_ALTFUNC:
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if (reset_gpio == 113)
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mode = 113 | GPIO_ALT_FN_2_OUT;
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if (reset_gpio == 95)
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mode = 95 | GPIO_ALT_FN_1_OUT;
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break;
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case RESETGPIO_FORCE_LOW:
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mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW;
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break;
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case RESETGPIO_FORCE_HIGH:
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mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH;
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break;
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};
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if (mode)
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pxa_gpio_mode(mode);
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}
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unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
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{
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unsigned short val = -1;
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@ -174,12 +137,11 @@ static inline void pxa_ac97_warm_pxa27x(void)
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{
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gsr_bits = 0;
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/* warm reset broken on Bulverde,
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so manually keep AC97 reset high */
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set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
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/* warm reset broken on Bulverde, so manually keep AC97 reset high */
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pxa27x_assert_ac97reset(reset_gpio, 1);
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udelay(10);
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GCR |= GCR_WARM_RST;
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set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
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pxa27x_assert_ac97reset(reset_gpio, 0);
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udelay(500);
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}
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@ -385,7 +347,7 @@ int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
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if (cpu_is_pxa27x()) {
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/* Use GPIO 113 as AC97 Reset on Bulverde */
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set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
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pxa27x_assert_ac97reset(reset_gpio, 0);
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ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
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if (IS_ERR(ac97conf_clk)) {
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ret = PTR_ERR(ac97conf_clk);
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