forked from luck/tmp_suning_uos_patched
sfc: Use rmb() to ensure reads occur in order
Enabling write-combining may also enable read reordering. The BIU is only guaranteed to read from a 128-bit CSR or 64-bit SRAM word when the host reads from its lowest address; otherwise the BIU may use the latched value. Therefore we need to reinstate the read memory barriers after the first read operation for each CSR or SRAM word. Signed-off-by; Ben Hutchings <bhutchings@solarflare.com>
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@ -152,6 +152,7 @@ static inline void efx_reado(struct efx_nic *efx, efx_oword_t *value,
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spin_lock_irqsave(&efx->biu_lock, flags);
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value->u32[0] = _efx_readd(efx, reg + 0);
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rmb();
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value->u32[1] = _efx_readd(efx, reg + 4);
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value->u32[2] = _efx_readd(efx, reg + 8);
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value->u32[3] = _efx_readd(efx, reg + 12);
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@ -174,6 +175,7 @@ static inline void efx_sram_readq(struct efx_nic *efx, void __iomem *membase,
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value->u64[0] = (__force __le64)__raw_readq(membase + addr);
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#else
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value->u32[0] = (__force __le32)__raw_readl(membase + addr);
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rmb();
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value->u32[1] = (__force __le32)__raw_readl(membase + addr + 4);
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#endif
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spin_unlock_irqrestore(&efx->biu_lock, flags);
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