This patch adds support System MMU which supports address transition
from virtual address to physical address. Basically, each hardware
block is connected System MMU block can use directly vitrual address
when it accesses physical memory not using physical address.
Signed-off-by: Donguk Ryu <du.ryu@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
[kgene.kim@samsung.com: removed useless codes]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch changes the clock registration code to use the s3c_register_clocks()
followed by s3c_disable_clocks() instead of the loops it was using and cleanups
the return of s3c24xx_register_clocks() because it includes it.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add IRQ and register base address definitions for MIPI CSI slave devices.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch modifies the following.
1. Moves the SROM controller mapping from S5PV210 specific code to
S5P common code. The SROM controller mapping can be used for all
S5P SoCs.
2. Define the SROM controller physical address for S5P64X0, S5P6442,
S5PC100, S5PV210 and S5PV310.
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The SROM register difinitions of S5PV310/S5PC210 (mach/regs-srom.h)
can be used to other S5P SoCs such as S5PV210/S5PC110. So moved into
plat/regs-srom.h of plat-s5p directory.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Universal (C210) board has 3 SDHCI devices.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
[kgene.kim@samsung.com: minor edit of title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support Power Domain for S5PV310 and S5PC210.
Signed-off-by: Changhwan Youn <chaos.youn at samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch is applied according to the commit 1a8e41cd67
(ARM: 6395/1: VExpress: Set bit 22 in the PL310 (cache controller) AuxCtlr register).
Actually, S5PV310 has same cache controller(PL310).
Following is from Catalin Marinas' commit.
Clearing bit 22 in the PL310 Auxiliary Control register (shared
attribute override enable) has the side effect of transforming Normal
Shared Non-cacheable reads into Cacheable no-allocate reads.
Coherent DMA buffers in Linux always have a Cacheable alias via the
kernel linear mapping and the processor can speculatively load cache
lines into the PL310 controller. With bit 22 cleared, Non-cacheable
reads would unexpectedly hit such cache lines leading to buffer
corruption.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Cc: <stable@kernel.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Kernel 2.6.37 adds new interrupt methods which take a struct irq_data
rather than an irq number. Begin converting Samsung platforms over to
these methods by converting s3c_irqext_wake() with a simple textual
substitution.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable I2S_0 device on the SMDKC210.
Also, add the dependency I2C_1 device.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[kgene.kim@samsung.com: minor changed title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable I2S_0 device on the SMDKV310.
Also, add the dependency I2C_1 device.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[kgene.kim@samsung.com: minor changed title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable AC97 audio device on SMDKV310 and SMDKC210.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Define missing controller clocks for the I2S-0, 1 and 2 blocks.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[kgene.kim@samsung.com: Added description]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Define clock for the AC97 controller.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Define PDMA clocks for the controller 0 and 1.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Enable the I2C1 device on SMDKV310 and SMDKC210.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[kgene.kim@samsung.com: minor changed title]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds ARCH_HAS_CPUFREQ in Kconfig of ARCH_S5PV310 and updates
Makefile for supporting build S5PV310 CPUFREQ driver.
Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
FOUT APLL clock is used as a source of ARM core clock. So we need that the
clock source can be changed dynamically by using CPUFREQ driver. This patch
can give correct frequency when calling clk_get_rate() function.
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Sangwook Ju <sw.ju@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch updates following of CPUFREQ.
- Updated DVFS table and divider value
- Added common function
- Added some function for changing APLL and setting
Signed-off-by: Sangwook Ju <sw.ju@samsung.com>
Reviewed-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support CPUFREQ driver for S5PV310 and S5PC210. This can
support DVFS(Dynamic Voltage and Frequency Scaling). The voltage scaling
depends on existence of regulator.
Sigend-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds DMC io mapping for access it and adds registers.
This is used in checking DRAM memory type.
Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds missing CMU(Clock Management Unit) registers for
updated S5PV310 CPUFREQ driver.
Signed-off-by: Sangwook Ju <sw.ju@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds CMU(Clock Management Unit) registers for S5PV310/S5PC210
CPUFREQ driver and modifies some register names according to datasheet.
Signed-off-by: Sunyoung Kang <sy0816.kang@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The 4 combiner groups use same registers to handle the interrupt.
In previous implementation, the whole registers are checked to find
which interupt is occurred and thus interrupt in other groups can
be detected. This patch adds irq_mask to solve this problem.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The irqs from SPI(0) to SPI(39) and SPI(51), SPI(53) are connected to the
interrupt combiner. This patch limits the irqs which should be initialized
to support cascade interrupt.
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Define platform devices for all audio devices found on S5PV310
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Samsung's Soc S5PV310 has three PL330 DMACs. First is dedicated for
Memory->Memory data transfer while the other two meant for data
transfer with peripherals.
Define and add latter two PL330 DMACs as platform devices on the
S5PV310 platform.
Signed-off-by: Jassi Brar <jassi.brar@samsung.com>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Liam Girdwood <lrg@slimlogic.co.uk>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds to support ethernet for SMDKV310 and SMDKC210 board.
- define smc911x resources
- define configurations of smc911x platform data
- define platform device "smsc911x"
- initialize srom controller for lan9215 chip
Signed-off-by: Daein Moon <moon9124@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds support SROMC for S5PV310 and S5PC210.
Signed-off-by: Daein Moon <moon9124@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch changes VMALLOC_END from 0xE0000000 to 0xF6000000, because
some systems want to use more vmalloc()/ioremap() area and now don't use
from at 0xE0000000 to 0xF6000000 (the start of Samsung SoCs' VA space)
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds EINT(External Interrupt) support on S5PV310 and S5PC210.
All EINTs are transferred to GIC through interrupt combiner.
Signed-off-by: Jongsun Han <jongsun.han@samsung.com>
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds the definition for both IRQs and GPIO registers for
external interrupts.
Signed-off-by: Jongsun Han <jongsun.han@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds L2 cache initialization code in cpu.c of ARCH_S5PV310.
It includes TAG and Data latency, Prefetch, and Power configurations.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Basically, need L2 cache initialize function in ARCH_S5PV310. So it would
be better to move it into ARCH_S5PV310 common part. This patch removes L2
cache initialization code at the each board file.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds GPIOlib support for S5PV310 and S5PC210.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
[kgene.kim@samsung.com: Fix NR_IRQS]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds initial map for GPIO2 and GPIO3.
S5PV310/S5PC210 has separated GPIO1, GPIO2 and GPIO3.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch updates MAX_COMBINER_NR from 39 to 40 because
S5PV310 need 39th combiner for including EINT16_31.
Signed-off-by: Jongpill Lee <boyko.lee@samsung.com>
Signed-off-by: Sangbeom Kim <sbkim73@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S5P Samsung SoCs has a EPLL to support various PLL clock sources for other
H/W blocks. Until now, to control EPLL, each of SoCs make their own functions
in 'mach-s5pxxx/clock.c'. But some of functions, 'xxx_epll_get_rate()' and
'xxx_epll_enable()', are exactly same in all S5P SoCs, so this patch move
these duplicated codes to common EPLL functions that use platform wide.
Signed-off-by: Seungwhan Youn <sw.youn@samsung.com>
Acked-by: Jassi Brar <jassi.brar@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
S5PV310 and S5PC210 support more I2C devices than previous SoCs.
Add the device support code for them.
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
