Commit Graph

159 Commits

Author SHA1 Message Date
Lennert Buytenhek
3f7e5815f4 [ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x
Split the iop3xx mach type into iop32x and iop33x -- split the config
symbols, and move the code in the mach-iop3xx directory to the mach-iop32x
and mach-iop33x directories.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:36 +01:00
Lennert Buytenhek
197c9444d6 [ARM] 3814/1: move 80200 dma_inv_range() erratum check out of line
On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
clear the dirty bits, which means that if we invalidate a dirty line,
the dirty data can still be written back to memory later on.

To work around this, dma_inv_range() on these two processors is
implemented as dma_flush_range() (i.e. do a clean D-cache line before
doing the invalidate D-cache line.)  For this, we currently have a
processor ID check in xscale_dma_inv_range(), but a better solution
is to add a separate cache_fns and proc_info for A0/A1 80200.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:27 +01:00
Lennert Buytenhek
51635ad282 [ARM] 3813/1: prevent >= 4G /dev/mem mmap()
Prevent userland from mapping in physical address regions >= 4G by
checking for that in valid_mmap_phys_addr_range().

Unfortunately, we cannot override valid_mmap_phys_addr_range() without
also overriding valid_phys_addr_range(), so copy drivers/char/mem.c's
version of valid_phys_addr_range() over to arch/arm/mm/mmap.c as well.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:26 +01:00
Russell King
d84b47115a [ARM] Move mmu.c out of the way
Rename mmu.c to context.c - it's the ARMv6 ASID context handling
code rather than generic "mmu" handling code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Russell King
1b2e2b73b4 [ARM] Cleanup arch/arm/mm a little
Move top_pmd into arch/arm/mm/mm.h - nothing outside arch/arm/mm
references it.

Move the repeated definition of TOP_PTE into mm/mm.h, as well as
a few function prototypes.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Dan Williams
36694a4c22 [ARM] 3780/1: Fix iop321 cpuid
Patch from Dan Williams

commit a6a38a6622 changed the iop321 id to a value that does not work with all platforms.  Change the mask to permit bit 11.  Tested on an iq80321 600Mhz CRB.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-14 17:45:16 +01:00
Catalin Marinas
f854d37ab6 [ARM] 3773/1: Add the HWCAP_VFP bit for the ARM926 CPUs
Patch from Catalin Marinas

The ARM926EJ-S CPU has the VFP coprocessor and therefore it should be shown
in the /proc/cpuinfo if CONFIG_VFP is enabled.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-06 19:03:28 +01:00
George G. Davis
a188ad2bc7 [ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches
Patch from George G. Davis

Resolve ARM1136 VIPT non-aliasing cache coherency issues observed when
using ptrace to set breakpoints and cleanup copy_{to,from}_user_page()
while we're here as requested by Russell King because "it's also far
too heavy on non-v6 CPUs".

NOTES:

1. Only access_process_vm() calls copy_{to,from}_user_page().
2. access_process_vm() calls get_user_pages() to pin down the "page".
3. get_user_pages() calls flush_dcache_page(page) which ensures cache
   coherency between kernel and userspace mappings of "page".  However
   flush_dcache_page(page) may not invalidate I-Cache over this range
   for all cases, specifically, I-Cache is not invalidated for the VIPT
   non-aliasing case.  So memory is consistent between kernel and user
   space mappings of "page" but I-Cache may still be hot over this
   range.  IOW, we don't have to worry about flush_cache_page() before
   memcpy().
4. Now, for the copy_to_user_page() case, after memcpy(), we must flush
   the caches so memory is consistent with kernel cache entries and
   invalidate the I-Cache if this mm region is executable.  We don't
   need to do anything after memcpy() for the copy_from_user_page()
   case since kernel cache entries will be invalidated via the same
   process above if we access "page" again.  The flush_ptrace_access()
   function (borrowed from SPARC64 implementation) is added to handle
   cache flushing after memcpy() for the copy_to_user_page() case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-02 18:43:20 +01:00
Lennert Buytenhek
260e98edc8 [ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers
Patch from Lennert Buytenhek

On armv4t systems, we have always compiled the kernel with -march=armv4
instead of -march=armv4t, which means that any use of bx will bomb out.

Commit ba9b5d7637 introduced the use of
bx in the kernel, which means we need to compile with -march=armv4t on
armv4t systems now.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-28 12:51:20 +01:00
Catalin Marinas
ceaccbd2a6 [ARM] 3734/1: Fix the unused variable warning in __iounmap()
Patch from Catalin Marinas

This patch adds #ifdef around some variables in the arch/arm/mm/ioremap.c
file.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:30 +01:00
George G. Davis
7b1df1985c [ARM] 3737/1: Export ARM copy/clear_user_page symbols
Patch from George G. Davis

As reported by various folks on the ARM Linux kernel mailing list,
the video-buf.ko driver has undefined references on all ARM machines
which use it as observed during `make modules`:

Warning: "v4wb_clear_user_page" [drivers/media/video/video-buf.ko] undefined!

Similar warnings exist for all ARM machines which use this driver.
So this change adds the missing EXPORT_SYMBOLs to allow using this
driver as a module.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:27 +01:00
Lennert Buytenhek
a6a38a6622 [ARM] 3736/1: xscale: don't mis-report 80219 as an iop32x
Patch from Lennert Buytenhek

The IOP 80219 xscale CPU is a stripped down version of the IOP32x.
But the fact that the 80219 and IOP32x are very similar doesn't mean
that they need to share a cpu table entry.  It's also somewhat confusing
for the end user to see the 80219 reported as an IOP32x, so this patch
splits the IOP32x cpu table entry to make a separate entry for the
80219.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:26 +01:00
Russell King
67f3a58856 [ARM] Fix warning in consistent.c
No need for 'cr' to be a local variable, which is unused in the
SMP case, and only used once in the UP case.  Just call get_cr()
directly.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 13:30:52 +01:00
Russell King
906243d07b [ARM] Fix bad asm instruction in proc-arm925.S
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:44:30 +01:00
Russell King
00eb0f6b65 [ARM] More missing proc-macros.S includes
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:36:07 +01:00
Lennert Buytenhek
7cddc39702 [ARM] 3708/2: fix SMP build after section ioremap changes
Patch from Lennert Buytenhek

Commit ff0daca525 broke the SMP build,
this patch fixes it up again.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:26:02 +01:00
Thomas Gleixner
bb8d5a55a5 [PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.S
For several proc-<cputype>.S files the include of proc-macros.S is
missing. Make it compile and work again.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-02 17:29:22 -07:00
Linus Torvalds
a8c4c20dfa Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...
2006-07-02 15:04:12 -07:00
Nicolas Pitre
2dc7667b9d [ARM] 3541/2: workaround for PXA27x erratum E7
Patch from Nicolas Pitre

According to the Intel PXA27x Processor Family Specification
Update document (doc.nr. 280071-009) erratum E7, some care must be taken
to locate the disabling and re-enabling of the MMU to the beginning of a
cache line to avoid problems in some circumstances.

Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this
up.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 21:29:32 +01:00
Russell King
3f8efdbe73 Merge nommu branch 2006-07-01 20:43:57 +01:00
Lennert Buytenhek
a069c896d0 [ARM] 3705/1: add supersection support to ioremap()
Patch from Lennert Buytenhek

Analogous to the previous patch that allows ioremap() to use section
mappings, this patch allows ioremap() to use supersection mappings.
Original patch by Deepak Saxena.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 19:58:20 +01:00
Linus Torvalds
22a3e233ca Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial:
  Remove obsolete #include <linux/config.h>
  remove obsolete swsusp_encrypt
  arch/arm26/Kconfig typos
  Documentation/IPMI typos
  Kconfig: Typos in net/sched/Kconfig
  v9fs: do not include linux/version.h
  Documentation/DocBook/mtdnand.tmpl: typo fixes
  typo fixes: specfic -> specific
  typo fixes in Documentation/networking/pktgen.txt
  typo fixes: occuring -> occurring
  typo fixes: infomation -> information
  typo fixes: disadvantadge -> disadvantage
  typo fixes: aquire -> acquire
  typo fixes: mecanism -> mechanism
  typo fixes: bandwith -> bandwidth
  fix a typo in the RTC_CLASS help text
  smb is no longer maintained

Manually merged trivial conflict in arch/um/kernel/vmlinux.lds.S
2006-06-30 15:39:30 -07:00
Christoph Lameter
df849a1529 [PATCH] zoned vm counters: conversion of nr_pagetables to per zone counter
Conversion of nr_page_table_pages to a per zone counter

[akpm@osdl.org: bugfix]
Signed-off-by: Christoph Lameter <clameter@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-30 11:25:35 -07:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Russell King
ff0daca525 [ARM] Add section support to ioremap
Allow section mappings to be setup using ioremap() and torn down
with iounmap().  This requires additional support in the MM
context switch to ensure that mappings are properly synchronised
when mapped in.

Based an original implementation by Deepak Saxena, reworked and
ARMv6 support added by rmk.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 22:14:30 +01:00
Russell King
8799ee9f49 [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 18:24:21 +01:00
Andrew Victor
8fc5ffa063 [ARM] 3675/2: Preparing for AT91SAM926 support
Patch from Andrew Victor

This prepares the way for adding support for the new Atmel AT91SAM926x
processors.

Major changes:
- Rename time.c to at91rm9200_time.c
- Rename common.c to at91rm9200.c
- Introduce ARCH_AT91, of which ARCH_AT91RM9200, ARCH_AT91SAM9260 and
ARCH_AT91SAM9261 are dependent.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 16:06:33 +01:00
Russell King
22b1908610 [ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache
enable and mmu enable bits in the control register, whereby if the data
cache is enabled, the MMU must also be enabled.  Enabling the data
cache without the MMU is an invalid combination.

However, there are CPUs where the data cache can be enabled without the
MMU.

In order to allow these CPUs to take advantage of that, provide a
method whereby each proc-*.S file defines the control regsiter value
for use with nommu (with the MMU disabled.)  Later on, when we add
support for enabling the MMU on these devices, we can adjust the
"crval" macro to also enable the data cache for nommu.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 15:09:57 +01:00
Russell King
264edb35ce [ARM] Remove yucky ifdefs to print "id(wb)BRR" suffix on CPU name
The "id(wb)BRR" suffix reports which CPU debugging options were (or
were not) selected at kernel build time.  Rather than have every
proc-*.S file implement this, report the control register value,
from which this information can be deduced.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 15:03:09 +01:00
Hyok S. Choi
d090dddaba [ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S
is not valid or needed to be avoided. i.g. switch_mm is not needed,
just returns and this makes the I & D caches are valid which shows
great improvement of performance including task switching and IPC.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:56 +01:00
Hyok S. Choi
3e36122595 [ARM] nommu: export flush_dcache_page()
This is a trivial patch to export flush_dcache_page in mm/nommu.c.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:53 +01:00
Russell King
092c1952e1 [ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu build
Remove fault-armv.o, mmap.o and mm-armv.o from uclinux builds - these
are concerned with MMU-ful operations, and as such are redundant for
uclinux.

Since this also removes iotable_init() and iotable_init() is used
extensively in the platform support files, just make it a no-op.

Based upon a couple of patches by Hyok.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:52 +01:00
Russell King
888e7bf166 [ARM] Remove TABLE_SIZE, and several unused function prototypes
TABLE_SIZE is never used in arch/arm/mm/init.c.  create_memmap_holes(),
memtable_init, and setup_io_desc() no longer exist in the kernel.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:51 +01:00
Russell King
e6b1b38c52 [ARM] nommu: Provide a simple flush_dcache_page implementation
nommu doesn't require a complex flush_dcache_page implementation
like the MMU-ful CPUs do, so provide a simplified version in nommu.c
and omit flush.c from the build as appropriate.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:50 +01:00
Russell King
5924486dc0 [ARM] nommu: add stubs for ioremap and friends
nommu doesn't have any form of remapping support, so ioremap, etc
become stubs which just return the casted address, doing nothing
else.

Move ioport_map(), ioport_unmap(), pci_iomap(), pci_iounmap()
into a separate file which is always built.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:48 +01:00
Hyok S. Choi
f9c21a6ee7 [ARM] nommu: avoid selecting TLB and CPU specific copy code
Since uclinux doesn't make use of the TLB, including the TLB
maintainence and CPU-optimised copypage functions does not
make sense.  Remove them.

(This is part of one of Hyok's patches.)

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:47 +01:00
Russell King
60b6cf6851 [ARM] nommu: we need the TLS register emulation for nommu mode
Since there can be no fixed location for the TLS value with nommu
systems, we must provide TLS register emulation in order to support
TLS binaries on CPUs without the thread register.

Part of a patch from Hyok S. Choi, and cleaned up by rmk.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:43 +01:00
Russell King
800d8b5c4b [ARM] Remove partial non-v6 binutils compatibility
proc-v6 contains some compatibility to be able to use the V6
"cps" instruction.  However, the kernel makes use of this
instruction elsewhere extensively, so there's no point keeping
this compatibility anymore.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:31:22 +01:00
Russell King
1b93a71755 [ARM] Remove LOADREGS macro
As for RETINSTR, LOADREGS is a left-over from the 26-bit days.
Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:23:45 +01:00
Ben Dooks
3434d9d9fc [ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
Patch from Ben Dooks

Select CONFIG_CPU_ARM926 when CONFIG_CPU_S3C2412 is
selected.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-24 21:21:28 +01:00
Sascha Hauer
bb6d8c8828 [ARM] 3567/2: arm: base support for Hilscher netX
Patch from Sascha Hauer

This patch adds the base support for Hilscher's netX network
processors.

Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-19 15:27:53 +01:00
Vitaly Wool
78818e477b [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support
Patch from Vitaly Wool

This patch adds basic chip support for PNX4008 ARM platform.
It's basically the same as the previous one, but with the rmk's
comments taken into account.

Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-18 16:16:55 +01:00
Deepak Saxena
5cedae9ca7 [PATCH] ARM: Fix XScale PMD setting
The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation
defined" and it must be set to zero on Intel XScale CPUs or the cache does
not behave properly. Found by Mike Rapoport while debugging a flash issue
on the PXA255:

	http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-05-31 16:27:44 -07:00
Deepak Saxena
e6ed89ac9f [PATCH] ARM: explicitly disable BTB on ixp2350
We don't enable the BTB on the ixp2350 as that can cause weird
crashes (erratum #42.)  However, some bootloaders enable the BTB,
which means that we have to disable the BTB explicitly.

Found thanks to Tom Rini.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-05-30 20:33:20 -07:00
Catalin Marinas
478922c2b3 [ARM] 3526/1: ioremap should use vunmap instead of vfree on ARM
Patch from Catalin Marinas

This patch modifies the __ioremap_pfn and __iounmap functions in
arch/arm/mm/ioremap.c to use vunmap instead of vfree.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-05-16 11:39:31 +01:00
Russell King
95f3df6bcb [ARM] Fix SA110/SA1100 cache flushing
We had two implementations for flushing the cache, which meant StrongARM
caches weren't being correctly flushed.  Fix this by always using the
v4wb_flush_kern_cache_all method, rather than duplicating it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-07 13:23:57 +01:00
Russell King
74d02fb954 [ARM] Move FLUSH_BASE macros to asm/arch/memory.h
FLUSH_BASE must be visible to arch/arm/mm/init.c in order for the
memory region to be setup.  Move these definitions from
asm-arm/arch-*/hardware.h into asm-arm/arch-*/memory.h where mm
stuff can see them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-07 13:22:21 +01:00
Lennert Buytenhek
23759dc643 [ARM] 3439/2: xsc3: add I/O coherency support
Patch from Lennert Buytenhek

This patch adds support for the I/O coherent cache available on the
xsc3.  The approach is to provide a simple API to determine whether the
chipset supports coherency by calling arch_is_coherent() and then
setting the appropriate system memory PTE and PMD bits.  In addition,
we call this API on dma_alloc_coherent() and dma_map_single() calls.
A generic version exists that will compile out all the coherency-related
code that is not needed on the majority of ARM systems.

Note that we do not check for coherency in the dma_alloc_writecombine()
function as that still requires a special PTE setting.  We also don't
touch dma_mmap_coherent() as that is a special ARM-only API that is by
definition only used on non-coherent system.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-02 00:07:39 +01:00
Lennert Buytenhek
b48340aff0 [ARM] 3425/1: xsc3: need to include pgtable-hwdef.h
Patch from Lennert Buytenhek

Adapt xsc3 to the changes in 74945c8616
(xsc3 was written before but merged after the latter went in.)

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-30 10:24:07 +01:00
Lennert Buytenhek
23bdf86aa0 [ARM] 3377/2: add support for intel xsc3 core
Patch from Lennert Buytenhek

This patch adds support for the new XScale v3 core.  This is an
ARMv5 ISA core with the following additions:

- L2 cache
- I/O coherency support (on select chipsets)
- Low-Locality Reference cache attributes (replaces mini-cache)
- Supersections (v6 compatible)
- 36-bit addressing (v6 compatible)
- Single instruction cache line clean/invalidate
- LRU cache replacement (vs round-robin)

I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
cores have separate errata and have to handle things like L2, so it
is simpler to keep it separate.

L2 cache support is currently a build option because the L2 enable
bit must be set before we enable the MMU and there is no easy way to
capture command line parameters at this point.

There are still optimizations that can be done such as using LLR for
copypage (in theory using the exisiting mini-cache code) but those
can be addressed down the road.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 21:00:40 +01:00