On XLPII CPUs, the L1D cache has to be flushed with regular cache
operations before enabling threads in a core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6276/
No change in logic, the changes are:
* cleanup some whitespace and comments
* remove confusing argument of SYS_CPU_COHERENT_BASE macro
* make the numerical labels in macros consistent
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6273/
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
usual for this cycle with lots of clean-up.
- Cross arch clean-up and consolidation of early DT scanning code.
- Clean-up and removal of arch prom.h headers. Makes arch specific
prom.h optional on all but Sparc.
- Addition of interrupts-extended property for devices connected to
multiple interrupt controllers.
- Refactoring of DT interrupt parsing code in preparation for deferred
probe of interrupts.
- ARM cpu and cpu topology bindings documentation.
- Various DT vendor binding documentation updates.
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Merge tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
"DeviceTree updates for 3.13. This is a bit larger pull request than
usual for this cycle with lots of clean-up.
- Cross arch clean-up and consolidation of early DT scanning code.
- Clean-up and removal of arch prom.h headers. Makes arch specific
prom.h optional on all but Sparc.
- Addition of interrupts-extended property for devices connected to
multiple interrupt controllers.
- Refactoring of DT interrupt parsing code in preparation for
deferred probe of interrupts.
- ARM cpu and cpu topology bindings documentation.
- Various DT vendor binding documentation updates"
* tag 'devicetree-for-3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (82 commits)
powerpc: add missing explicit OF includes for ppc
dt/irq: add empty of_irq_count for !OF_IRQ
dt: disable self-tests for !OF_IRQ
of: irq: Fix interrupt-map entry matching
MIPS: Netlogic: replace early_init_devtree() call
of: Add Panasonic Corporation vendor prefix
of: Add Chunghwa Picture Tubes Ltd. vendor prefix
of: Add AU Optronics Corporation vendor prefix
of/irq: Fix potential buffer overflow
of/irq: Fix bug in interrupt parsing refactor.
of: set dma_mask to point to coherent_dma_mask
of: add vendor prefix for PHYTEC Messtechnik GmbH
DT: sort vendor-prefixes.txt
of: Add vendor prefix for Cadence
of: Add empty for_each_available_child_of_node() macro definition
arm/versatile: Fix versatile irq specifications.
of/irq: create interrupts-extended property
microblaze/pci: Drop PowerPC-ism from irq parsing
of/irq: Create of_irq_parse_and_map_pci() to consolidate arch code.
of/irq: Use irq_of_parse_and_map()
...
The early_init_devtree() API was removed in linux-next for 3.13 with
commit "mips: use early_init_dt_scan". This causes Netlogic XLP compile
to fail:
arch/mips/netlogic/xlp/setup.c:101: undefined reference to `early_init_devtree'
Add xlp_early_init_devtree() which uses the __dt_setup_arch() to
handle early device tree related initialization to fix this.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Panic() is going to add a \n itself and it's annoying if a panic message rolls
of the screen on a device with no scrollback.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Replace hardcoded CP0 PRId and CP1 FPIR register access masks throughout.
The change does not touch places that use shifted or partial masks.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5838/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add a default built-in device tree for XLP2xx SoC. The new file
xlp_fvp.dts has updated entries for I2C and memory.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5705/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add USB intialization code to handle the new XLP2XX USB 3.0 block.
This adds xlp/usb-init-xlp2.c to initialize the XLP2XX USB glue-logic
for XHCI and EHCI. Interrupt and IO offset code in xlp-hal/iomap.h
and xlp/nlm_hal.c is also updated for the new USB block.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5744/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
XLP2xx has a new I2C controller which has 4 buses connected to
it. Update the IO offset and IRQ mapping code to reflect this.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5707/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
On XLP2xx, wakeup code does not need to enable clock on the core.
Update xlp/wakeup.c to handle this.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5703/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add code to calculate the CPU and PIC frequency for XLP2XX SoCs.
Since the PIC frequency on XLP2XX can be configured, add a new macro
pic_timer_freq() to be used in netlogic/common/time.c.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: Ganesan Ramalingam <ganesanr@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5701/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The config7/config4 register has to be written on all the threads.
This does not cause any problems in XLP, but is needed for XLPII
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5700/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
XLP2XX is first in the series of 28nm XLPII processors.
The changes are to:
* Add processor ID for XLP2XX to asm/cpu.h and kernel/cpu-probe.c.
* Add a cpu_is_xlpii() function to check for XLPII processors.
* Update xlp_mmu_init() to use config4 to enable extended TLB.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5698/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Do not pass a memory section in the built-in DTB, and let the
boot code use the values from the DRAM BARs.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5699/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Read the memory from the Bridge DRAM BARs, if it is not passed in
from the device tree. This will allow us to remove memory configuration
from built in device trees.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5743/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Pull MIPS fixes from Ralf Baechle:
"MIPS fixes for 3.11. Half of then is for Netlogic the remainder
touches things across arch/mips.
Nothing really dramatic and by rc1 standards MIPS will be in fairly
good shape with this applied. Tested by building all MIPS defconfigs
of which with this pull request four platforms won't build. And yes,
it boots also on my favorite test systems"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
MIPS: kvm: Kconfig: Drop HAVE_KVM dependency from VIRTUALIZATION
MIPS: Octeon: Fix DT pruning bug with pip ports
MIPS: KVM: Mark KVM_GUEST (T&E KVM) as BROKEN_ON_SMP
MIPS: tlbex: fix broken build in v3.11-rc1
MIPS: Netlogic: Add XLP PIC irqdomain
MIPS: Netlogic: Fix USB block's coherent DMA mask
MIPS: tlbex: Fix typo in r3000 tlb store handler
MIPS: BMIPS: Fix thinko to release slave TP from reset
MIPS: Delete dead invocation of exception_exit().
Add a legacy irq domain for the XLP PIC interrupts. This will be used
when interrupts are assigned from the device tree. This change is required
after commit c5cdc67 "irqdomain: Remove temporary MIPS workaround code".
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: Jayachandran C <jchandra@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/5597/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The on-chip USB controller on Netlogic XLP does not suppport
DMA beyond 32-bit physical address. Set the coherent_dma_mask
of the USB in its PCI fixup to support this.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C. <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix an issue in plat_irq_dispatch due to which it can call do_IRQ
with a PIC irq that is not mapped.
When a per-cpu interrupt and a PIC interrupt are both active, the
check 'eirr & PERCPU_IRQ_MASK' will be true, but the interrupt in 'i'
will be the number of the PIC interrupt. In this case, we will call
do_IRQ on the PIC interrupt without mapping it with nlm_irq_to_xirq().
Fix this by using __ffs64 instead of __ilog2_u64 and using the
interrupt number instead of mask to identify per-cpu interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5432/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The XLPs in production do not need these workarounds. Remove the code and
the associated ifdef.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5430/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix a cache error found in stress test, caused by the prefetch instruction
going beyond valid memory when acessing the last page of a region. Add
the pref_backup logic similar to XLR in XLP too.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5431/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Earlier we just waited for the first thread of the CPU to come online
before proceeding to wake up others. Update it to wait for all the CPUs
in the core. This will be useful when the boot-up is slow, like while
debugging or when running in a simulator.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5429/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Fix an issue in the reset code. Since this code is copied to the
reset vector, using 'j' for looping is not correct. Use relative
branch 'b'.
Update the usage of 'j' in smpboot.S to be consistent although it
is not a bug there.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5427/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Move the nlm_cpu_ready[] array used by the cpu wakeup code to the
boot area, along with rest of the boot parameter code.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5425/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This moves the calculation and casting needed to access the CPU initialization
data to a function nlm_get_boot_data()
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5426/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The core initialization and reset vector setup needs to be done
even when booting uniprocessor. Move this code from smp.c to setup.c
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5428/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The reset and core initialization code should be available for
uniprocessor as well. This changes is just to take out the code
into a different file, without any change to the logic.
The change for uniprocessor initialization code is in a later patch.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5423/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Create new flle arch/mips/netlogic/xlp/dt.c and move the device
tree related code there.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5422/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add COP2 register state structure and functions for Netlogic XLP. The
RX and TX buffers and status registers are to be saved. Since the
registers are 64-bit, do the implementation in inline assembly which
works on both 32-bit and 64-bit kernels.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: ddaney.cavm@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5413/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Rename macro nlm_cop2_enable() to nlm_cop2_enable_irqsave() and the macro
nlm_cop2_restore to nlm_cop2_disable_irqrestore(). The new names will
reflect the functionality better, and will make nlm_cop2_restore()
available to be used later in COP2 save/restore patch.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: ddaney.cavm@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5412/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The sel argument os nlm_read_c2_status() was not used and the macro
returned the sel 0 in all cases. Fix this by defining two macros:
nlm_read_c2_status0() and nlm_read_c2_status1() to return the two
status registers.
Add functions to write to the status registers as well.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: ddaney.cavm@gmail.com
Patchwork: https://patchwork.linux-mips.org/patch/5414/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Add SWIOTLB config option and related files to Netlogic platform.
Some XLP SoC components like the SD/MMC interface cannot do DMA beyond
32-bit physical address. The SD/MMC driver can use memory outside this
range for IO, to support this we have to add bounce buffers implemented
by SWIOTLB.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Cc: Ganesan Ramalingam <ganesanr@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/5410/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The definitions are not used anywhere else, and merging it will
make adding the new USB definitions for XLPII series easier.
While there, cleanup some whitespace in usb-init.c. There is no
change to logic due to this commit.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5027/
Acked-by: John Crispin <blogic@openwrt.org>
This enables us to have a default device tree per SoC family to be built
into the kernel. The default device tree for XLP3xx has been added as part
of this change. Later this can be used to provide support default boards
for XLP2xx and XLP9xx SoCs.
Kconfig options are provided for each default device tree so that just the
needed ones can be selected to be built into the kernel.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5023/
Acked-by: John Crispin <blogic@openwrt.org>
The index for a device interrupt in the PIC interrupt routing table
changes for different chips in the XLP family. Avoid using the fixed
entries and derive the index value from the SoC device header.
Add workarounds for some devices which do not report the IRT index
correctly.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5025/
Acked-by: John Crispin <blogic@openwrt.org>
Use standard function to print cpumask. Also fixup the name of the
variable used and make it static.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5024/
Acked-by: John Crispin <blogic@openwrt.org>
On multi-chip boards, the first core on slave SoCs may take much
more time to wakeup. Add code to wait for the core to come up before
proceeding with the rest of the boot up.
Update xlp_wakeup_core to also skip the boot node and the boot CPU
initialization which is already complete.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4783/
Signed-off-by: John Crispin <blogic@openwrt.org>
Doing calibrate delay on a hardware thread will be inaccurate since
it depends on the load on other threads in the core. It will also
slow down the boot process when done for 128 hardware threads. Switch
to a pre-computed loops per jiffy based on the core frequency. The
value is computed based on the core frequency and roughly matches the
value calculated by calibrate_delay().
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4791/
Signed-off-by: John Crispin <blogic@openwrt.org>
The XLR/XLS/XLP PIC has a 8 countdown timers which run at the PIC
frequencey. One of these can be used as a clocksource to provide
timestamps that is common across cores. This can be used in place
of the count/compare clocksource which is per-CPU.
On XLR/XLS PIC registers are 32-bit, so we just use the lower 32-bits
of the PIC counter. On XLP, the whole 64-bit can be used.
Provide common macros and functions for PIC timer registers on XLR/XLS
and XLP, and use them to register a PIC clocksource.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4786/
Signed-off-by: John Crispin <blogic@openwrt.org>
Since we now use r4k cache code for Netlogic XLP, it is
better to split L1 icache among the active threads, so that
threads won't step on each other while flushing icache.
The L1 dcache is already split among the threads in the core.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4787/
Signed-off-by: John Crispin <blogic@openwrt.org>
Provide functions ack_c0_eirr(), set_c0_eimr(), clear_c0_eimr()
and read_c0_eirr_and_eimr() that do the EIMR and EIRR operations
and update the interrupt handling code to use these functions.
Also, use the EIMR register functions to mask interrupts in the
irq code.
The 64-bit interrupt request and mask registers (EIRR and EIMR) are
accessed when the interrupts are off, and the common operations are
to set or clear a bit in these registers. Using the 64-bit c0 access
functions for these operations is not optimal in 32-bit, because it
will disable/restore interrupts and split/join the 64-bit value during
each register access.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4790/
Signed-off-by: John Crispin <blogic@openwrt.org>
Add support for XLS6xx CPUs to the Fast Message Network (FMN)
configuration.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4785/
Signed-off-by: John Crispin <blogic@openwrt.org>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The commit 2a37b1a "MIPS: Netlogic: Move from u32 cpumask to cpumask_t"
breaks uniprocessor compilation on XLR with:
arch/mips/netlogic/xlr/setup.c: In function 'prom_init':
arch/mips/netlogic/xlr/setup.c:196:6: error: unused variable 'i'
Fix by defining 'i' only when CONFIG_SMP is defined.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/4760/
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
