forked from luck/tmp_suning_uos_patched
0008c1f3bc
An optional devicetree property was added to the imx-weim driver, which if present instructs it to operate in burst clock mode. Update the dt-bindings to reflect this. Signed-off-by: Sven Van Asbroeck <TheSven73@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
113 lines
3.8 KiB
Plaintext
113 lines
3.8 KiB
Plaintext
Device tree bindings for i.MX Wireless External Interface Module (WEIM)
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The term "wireless" does not imply that the WEIM is literally an interface
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without wires. It simply means that this module was originally designed for
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wireless and mobile applications that use low-power technology.
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The actual devices are instantiated from the child nodes of a WEIM node.
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Required properties:
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- compatible: Should contain one of the following:
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"fsl,imx1-weim"
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"fsl,imx27-weim"
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"fsl,imx51-weim"
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"fsl,imx50-weim"
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"fsl,imx6q-weim"
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- reg: A resource specifier for the register space
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(see the example below)
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- clocks: the clock, see the example below.
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- #address-cells: Must be set to 2 to allow memory address translation
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- #size-cells: Must be set to 1 to allow CS address passing
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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<cs-number> 0 <physical address of mapping> <size>
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Optional properties:
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- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
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devices, it should be the phandle to the system General
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Purpose Register controller that contains WEIM CS GPR
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register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
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should be set up as one of the following 4 possible
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values depending on the CS space configuration.
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IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
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---------------------------------------------
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05 128M 0M 0M 0M
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033 64M 64M 0M 0M
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0113 64M 32M 32M 0M
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01111 32M 32M 32M 32M
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In case that the property is absent, the reset value or
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what bootloader sets up in IOMUXC_GPR1[11:0] will be
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used.
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- fsl,burst-clk-enable For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
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devices, the presence of this property indicates that
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the weim bus should operate in Burst Clock Mode.
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Timing property for child nodes. It is mandatory, not optional.
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- fsl,weim-cs-timing: The timing array, contains timing values for the
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child node. We get the CS indexes from the address
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ranges in the child node's "reg" property.
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The number of registers depends on the selected chip:
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For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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registers: CSxU, CSxL.
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For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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there are three registers: CSCRxU, CSCRxL, CSCRxA.
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For i.MX50, i.MX53 ("fsl,imx50-weim"),
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i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
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there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
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CSxRCR2, CSxWCR1, CSxWCR2.
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Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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weim: weim@21b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x08000000>;
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fsl,weim-cs-gpr = <&gpr>;
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x02000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <2>;
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fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
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0x0000c000 0x1404a38e 0x00000000>;
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};
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};
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Example for an imx6q-based board, a multi-chipselect device connected to WEIM:
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In this case, both chip select 0 and 1 will be configured with the same timing
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array values.
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weim: weim@21b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x02000000
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1 0 0x0a000000 0x02000000
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2 0 0x0c000000 0x02000000
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3 0 0x0e000000 0x02000000>;
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fsl,weim-cs-gpr = <&gpr>;
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acme@0 {
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compatible = "acme,whatever";
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reg = <0 0 0x100>, <0 0x400000 0x800>,
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<1 0x400000 0x800>;
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fsl,weim-cs-timing = <0x024400b1 0x00001010 0x20081100
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0x00000000 0xa0000240 0x00000000>;
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};
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};
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