forked from luck/tmp_suning_uos_patched
0006fd63d1
On DRA7xx, DISPC needs to write output signal polarities not only to a DISPC register, like for all earlier DSS versions, but to control module's CTRL_CORE_SMA_SW_1 register. This patch adds support to write the polarities to control module. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> |
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backlight | ||
console | ||
fbdev | ||
logo | ||
display_timing.c | ||
hdmi.c | ||
Kconfig | ||
Makefile | ||
of_display_timing.c | ||
of_videomode.c | ||
vgastate.c | ||
videomode.c |