forked from luck/tmp_suning_uos_patched
b75bb2365d
The icache invalidate functions should disable the icache on AM33 and wait for it to quiesce before attempting to invalidate it, and should then wait for it to quiesce again before reenabling it, but on AM34 they should invalidate directly. The same goes for the dcache invalidation, but this isn't used much. Whilst we're at it, this can be wrapped in assembler macros to remove duplicate code. The AM33 manual states that: An operation that invalidates the cache, switches the writing mode, or changes the way mode must be performed after disabling the cache, checking the busy bit, and confirming that the cache is not in operation. for the dcache [sec 2.8.3.2.1]. This is not stated so for the icache [sec 2.8.3.1.1] but the example code there suggests that it is. Whilst the AM34 manual states that the cache must be disabled for both the icache [sec 1.8.3.2.1] and the dcache [sec 1.8.3.2.1], the Panasonic hardware engineers say the manual is wrong and that disabling the caches for invalidation is wrong. Furthermore, they say that disabling the caches on the AM34 whilst running an SMP kernel can lead to incoherency between the various CPU caches and should thus be avoided. Signed-off-by: David Howells <dhowells@redhat.com>
134 lines
2.6 KiB
PHP
134 lines
2.6 KiB
PHP
/* MN10300 CPU core caching macros -*- asm -*-
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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###############################################################################
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#
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# Invalidate the instruction cache.
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# A0: Should hold CHCTR
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# D0: Should have been read from CHCTR
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# D1: Will be clobbered
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#
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# On some cores it is necessary to disable the icache whilst we do this.
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#
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###############################################################################
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.macro invalidate_icache,disable_irq
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#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
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.if \disable_irq
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# don't want an interrupt routine seeing a disabled cache
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mov epsw,d1
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and ~EPSW_IE,epsw
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or EPSW_NMID,epsw
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nop
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nop
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.endif
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# disable the icache
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and ~CHCTR_ICEN,d0
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movhu d0,(a0)
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# and wait for it to calm down
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setlb
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movhu (a0),d0
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btst CHCTR_ICBUSY,d0
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lne
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# invalidate
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or CHCTR_ICINV,d0
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movhu d0,(a0)
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# wait for the cache to finish
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setlb
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movhu (a0),d0
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btst CHCTR_ICBUSY,d0
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lne
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# and reenable it
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or CHCTR_ICEN,d0
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movhu d0,(a0)
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movhu (a0),d0
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.if \disable_irq
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LOCAL_IRQ_RESTORE(d1)
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.endif
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#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
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# invalidate
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or CHCTR_ICINV,d0
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movhu d0,(a0)
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movhu (a0),d0
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#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
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.endm
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###############################################################################
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#
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# Invalidate the data cache.
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# A0: Should hold CHCTR
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# D0: Should have been read from CHCTR
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# D1: Will be clobbered
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#
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# On some cores it is necessary to disable the dcache whilst we do this.
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#
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###############################################################################
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.macro invalidate_dcache,disable_irq
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#if defined(CONFIG_AM33_2) || defined(CONFIG_AM33_3)
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.if \disable_irq
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# don't want an interrupt routine seeing a disabled cache
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mov epsw,d1
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and ~EPSW_IE,epsw
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or EPSW_NMID,epsw
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nop
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nop
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.endif
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# disable the dcache
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and ~CHCTR_DCEN,d0
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movhu d0,(a0)
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# and wait for it to calm down
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setlb
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movhu (a0),d0
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btst CHCTR_DCBUSY,d0
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lne
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# invalidate
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or CHCTR_DCINV,d0
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movhu d0,(a0)
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# wait for the cache to finish
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setlb
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movhu (a0),d0
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btst CHCTR_DCBUSY,d0
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lne
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# and reenable it
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or CHCTR_DCEN,d0
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movhu d0,(a0)
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movhu (a0),d0
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.if \disable_irq
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LOCAL_IRQ_RESTORE(d1)
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.endif
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#else /* CONFIG_AM33_2 || CONFIG_AM33_3 */
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# invalidate
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or CHCTR_DCINV,d0
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movhu d0,(a0)
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movhu (a0),d0
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#endif /* CONFIG_AM33_2 || CONFIG_AM33_3 */
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.endm
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