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This converts the plain text documentation to reStructuredText format and add it to Sphinx TOC tree. No essential content change. Signed-off-by: Changbin Du <changbin.du@gmail.com> Reviewed-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Signed-off-by: Jonathan Corbet <corbet@lwn.net>
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.. SPDX-License-Identifier: GPL-2.0
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==============
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Kernel Entries
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==============
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This file documents some of the kernel entries in
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arch/x86/entry/entry_64.S. A lot of this explanation is adapted from
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an email from Ingo Molnar:
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http://lkml.kernel.org/r/<20110529191055.GC9835%40elte.hu>
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The x86 architecture has quite a few different ways to jump into
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kernel code. Most of these entry points are registered in
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arch/x86/kernel/traps.c and implemented in arch/x86/entry/entry_64.S
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for 64-bit, arch/x86/entry/entry_32.S for 32-bit and finally
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arch/x86/entry/entry_64_compat.S which implements the 32-bit compatibility
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syscall entry points and thus provides for 32-bit processes the
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ability to execute syscalls when running on 64-bit kernels.
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The IDT vector assignments are listed in arch/x86/include/asm/irq_vectors.h.
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Some of these entries are:
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- system_call: syscall instruction from 64-bit code.
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- entry_INT80_compat: int 0x80 from 32-bit or 64-bit code; compat syscall
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either way.
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- entry_INT80_compat, ia32_sysenter: syscall and sysenter from 32-bit
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code
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- interrupt: An array of entries. Every IDT vector that doesn't
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explicitly point somewhere else gets set to the corresponding
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value in interrupts. These point to a whole array of
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magically-generated functions that make their way to do_IRQ with
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the interrupt number as a parameter.
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- APIC interrupts: Various special-purpose interrupts for things
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like TLB shootdown.
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- Architecturally-defined exceptions like divide_error.
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There are a few complexities here. The different x86-64 entries
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have different calling conventions. The syscall and sysenter
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instructions have their own peculiar calling conventions. Some of
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the IDT entries push an error code onto the stack; others don't.
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IDT entries using the IST alternative stack mechanism need their own
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magic to get the stack frames right. (You can find some
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documentation in the AMD APM, Volume 2, Chapter 8 and the Intel SDM,
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Volume 3, Chapter 6.)
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Dealing with the swapgs instruction is especially tricky. Swapgs
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toggles whether gs is the kernel gs or the user gs. The swapgs
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instruction is rather fragile: it must nest perfectly and only in
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single depth, it should only be used if entering from user mode to
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kernel mode and then when returning to user-space, and precisely
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so. If we mess that up even slightly, we crash.
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So when we have a secondary entry, already in kernel mode, we *must
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not* use SWAPGS blindly - nor must we forget doing a SWAPGS when it's
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not switched/swapped yet.
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Now, there's a secondary complication: there's a cheap way to test
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which mode the CPU is in and an expensive way.
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The cheap way is to pick this info off the entry frame on the kernel
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stack, from the CS of the ptregs area of the kernel stack::
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xorl %ebx,%ebx
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testl $3,CS+8(%rsp)
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je error_kernelspace
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SWAPGS
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The expensive (paranoid) way is to read back the MSR_GS_BASE value
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(which is what SWAPGS modifies)::
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movl $1,%ebx
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movl $MSR_GS_BASE,%ecx
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rdmsr
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testl %edx,%edx
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js 1f /* negative -> in kernel */
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SWAPGS
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xorl %ebx,%ebx
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1: ret
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If we are at an interrupt or user-trap/gate-alike boundary then we can
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use the faster check: the stack will be a reliable indicator of
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whether SWAPGS was already done: if we see that we are a secondary
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entry interrupting kernel mode execution, then we know that the GS
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base has already been switched. If it says that we interrupted
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user-space execution then we must do the SWAPGS.
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But if we are in an NMI/MCE/DEBUG/whatever super-atomic entry context,
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which might have triggered right after a normal entry wrote CS to the
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stack but before we executed SWAPGS, then the only safe way to check
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for GS is the slower method: the RDMSR.
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Therefore, super-atomic entries (except NMI, which is handled separately)
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must use idtentry with paranoid=1 to handle gsbase correctly. This
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triggers three main behavior changes:
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- Interrupt entry will use the slower gsbase check.
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- Interrupt entry from user mode will switch off the IST stack.
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- Interrupt exit to kernel mode will not attempt to reschedule.
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We try to only use IST entries and the paranoid entry code for vectors
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that absolutely need the more expensive check for the GS base - and we
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generate all 'normal' entry points with the regular (faster) paranoid=0
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variant.
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