Ma Ling 044c7c415a drm/i915: Use documented PLL timing limits for G4X platform ... The values come from the internal reference spreadsheet on PLL timing limits for the G4X chipsets. Part of fixing fd.o bug #17508 Signed-off-by: Ma Ling <ling.ma@intel.com> [anholt: Cleaned up some whitespace] Signed-off-by: Eric Anholt <eric@anholt.net>		2009-03-27 14:45:11 -07:00
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drm	drm/i915: Use documented PLL timing limits for G4X platform	2009-03-27 14:45:11 -07:00
Makefile	drm: reorganise drm tree to be more future proof.	2008-07-14 10:45:01 +10:00