forked from luck/tmp_suning_uos_patched
c41b16f8c9
Consolidate the FPGA IRQ handling code. Integrator/AP and Versatile have one FPGA-based IRQ handler each. Integrator/CP has three. Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
73 lines
1.6 KiB
C
73 lines
1.6 KiB
C
/*
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* Support for Versatile FPGA-based IRQ controllers
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*/
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <asm/mach/irq.h>
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#include <plat/fpga-irq.h>
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#define IRQ_STATUS 0x00
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#define IRQ_RAW_STATUS 0x04
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#define IRQ_ENABLE_SET 0x08
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#define IRQ_ENABLE_CLEAR 0x0c
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static void fpga_irq_mask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - f->irq_start);
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writel(mask, f->base + IRQ_ENABLE_CLEAR);
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}
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static void fpga_irq_unmask(struct irq_data *d)
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{
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struct fpga_irq_data *f = irq_data_get_irq_chip_data(d);
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u32 mask = 1 << (d->irq - f->irq_start);
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writel(mask, f->base + IRQ_ENABLE_SET);
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}
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static void fpga_irq_handle(unsigned int irq, struct irq_desc *desc)
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{
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struct fpga_irq_data *f = get_irq_desc_data(desc);
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u32 status = readl(f->base + IRQ_STATUS);
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if (status == 0) {
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do_bad_IRQ(irq, desc);
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return;
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}
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do {
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irq = ffs(status) - 1;
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status &= ~(1 << irq);
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generic_handle_irq(irq + f->irq_start);
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} while (status);
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}
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void __init fpga_irq_init(int parent_irq, u32 valid, struct fpga_irq_data *f)
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{
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unsigned int i;
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f->chip.irq_ack = fpga_irq_mask;
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f->chip.irq_mask = fpga_irq_mask;
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f->chip.irq_unmask = fpga_irq_unmask;
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if (parent_irq != -1) {
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set_irq_data(parent_irq, f);
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set_irq_chained_handler(parent_irq, fpga_irq_handle);
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}
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for (i = 0; i < 32; i++) {
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if (valid & (1 << i)) {
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unsigned int irq = f->irq_start + i;
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set_irq_chip_data(irq, f);
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set_irq_chip(irq, &f->chip);
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set_irq_handler(irq, handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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}
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}
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}
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