forked from luck/tmp_suning_uos_patched
0577bb661e
When handling Interrupt Source Override in MADT table, the default ISA IRQ trigger model and polarity should be edge-rising. Current IA64 implmentation doesn't follow the specification and set default ISA IRQ trigger model as level-low. With that wrong configuration and when system runs out of interrupt vectors, it will cause vector sharing among edge triggered ISA IRQ and level triggered PCI IRQ, then interrupt storm. So change the code to follow the specification. Signed-off-by: Liu Jiang <jiang.liu@huawei.com> Signed-off-by: Tony Luck <tony.luck@intel.com> |
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| alpha | ||
| arm | ||
| avr32 | ||
| blackfin | ||
| c6x | ||
| cris | ||
| frv | ||
| h8300 | ||
| hexagon | ||
| ia64 | ||
| m32r | ||
| m68k | ||
| microblaze | ||
| mips | ||
| mn10300 | ||
| openrisc | ||
| parisc | ||
| powerpc | ||
| s390 | ||
| score | ||
| sh | ||
| sparc | ||
| tile | ||
| um | ||
| unicore32 | ||
| x86 | ||
| xtensa | ||
| .gitignore | ||
| Kconfig | ||