forked from luck/tmp_suning_uos_patched
c8c90860cd
Commit 81d11955bf ("ARM: 6405/1: Handle __flush_icache_all for
CONFIG_SMP_ON_UP") added a new function to struct cpu_cache_fns:
flush_icache_all(). It also implemented this for v6 and v7 but not
for v5 and backwards. Without the function pointer in place, we
will be calling wrong cache functions.
For example with ep93xx we get following:
Unable to handle kernel paging request at virtual address ee070f38
pgd = c0004000
[ee070f38] *pgd=00000000
Internal error: Oops: 80000005 [#1] PREEMPT
last sysfs file:
Modules linked in:
CPU: 0 Not tainted (2.6.36+ #1)
PC is at 0xee070f38
LR is at __dma_alloc+0x11c/0x2d0
pc : [<ee070f38>] lr : [<c0032c8c>] psr: 60000013
sp : c581bde0 ip : 00000000 fp : c0472000
r10: c0472000 r9 : 000000d0 r8 : 00020000
r7 : 0001ffff r6 : 00000000 r5 : c0472400 r4 : c5980000
r3 : c03ab7e0 r2 : 00000000 r1 : c59a0000 r0 : c5980000
Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: c000717f Table: c0004000 DAC: 00000017
Process swapper (pid: 1, stack limit = 0xc581a270)
[<c0032c8c>] (__dma_alloc+0x11c/0x2d0)
[<c0032e5c>] (dma_alloc_writecombine+0x1c/0x24)
[<c0204148>] (ep93xx_pcm_preallocate_dma_buffer+0x44/0x60)
[<c02041c0>] (ep93xx_pcm_new+0x5c/0x88)
[<c01ff188>] (snd_soc_instantiate_cards+0x8a8/0xbc0)
[<c01ff59c>] (soc_probe+0xfc/0x134)
[<c01adafc>] (platform_drv_probe+0x18/0x1c)
[<c01acca4>] (driver_probe_device+0xb0/0x16c)
[<c01ac284>] (bus_for_each_drv+0x48/0x84)
[<c01ace90>] (device_attach+0x50/0x68)
[<c01ac0f8>] (bus_probe_device+0x24/0x44)
[<c01aad7c>] (device_add+0x2fc/0x44c)
[<c01adfa8>] (platform_device_add+0x104/0x15c)
[<c0015eb8>] (simone_init+0x60/0x94)
[<c0021410>] (do_one_initcall+0xd0/0x1a4)
__dma_alloc() calls (inlined) __dma_alloc_buffer() which ends up
calling dmac_flush_range(). Now since the entries in the
arm920_cache_fns are shifted by one, we jump into address 0xee070f38
which is actually next instruction after the arm920_cache_fns
structure.
So implement flush_icache_all() for the rest of the supported CPUs
using a generic 'invalidate I cache' instruction.
Signed-off-by: Mika Westerberg <mika.westerberg@iki.fi>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
405 lines
10 KiB
ArmAsm
405 lines
10 KiB
ArmAsm
/*
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* linux/arch/arm/mm/arm940.S: utility functions for ARM940T
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*
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* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/hwcap.h>
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#include <asm/pgtable-hwdef.h>
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#include <asm/pgtable.h>
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#include <asm/ptrace.h>
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#include "proc-macros.S"
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/* ARM940T has a 4KB DCache comprising 256 lines of 4 words */
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#define CACHE_DLINESIZE 16
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#define CACHE_DSEGMENTS 4
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#define CACHE_DENTRIES 64
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.text
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/*
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* cpu_arm940_proc_init()
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* cpu_arm940_switch_mm()
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*
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* These are not required.
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*/
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ENTRY(cpu_arm940_proc_init)
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ENTRY(cpu_arm940_switch_mm)
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mov pc, lr
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/*
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* cpu_arm940_proc_fin()
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*/
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ENTRY(cpu_arm940_proc_fin)
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mrc p15, 0, r0, c1, c0, 0 @ ctrl register
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bic r0, r0, #0x00001000 @ i-cache
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bic r0, r0, #0x00000004 @ d-cache
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mcr p15, 0, r0, c1, c0, 0 @ disable caches
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mov pc, lr
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/*
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* cpu_arm940_reset(loc)
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* Params : r0 = address to jump to
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* Notes : This sets up everything for a reset
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*/
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ENTRY(cpu_arm940_reset)
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ flush I cache
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mrc p15, 0, ip, c1, c0, 0 @ ctrl register
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bic ip, ip, #0x00000005 @ .............c.p
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bic ip, ip, #0x00001000 @ i-cache
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mcr p15, 0, ip, c1, c0, 0 @ ctrl register
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mov pc, r0
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/*
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* cpu_arm940_do_idle()
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*/
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.align 5
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ENTRY(cpu_arm940_do_idle)
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mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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/*
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* flush_icache_all()
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*
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* Unconditionally clean and invalidate the entire icache.
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*/
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ENTRY(arm940_flush_icache_all)
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mov pc, lr
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ENDPROC(arm940_flush_icache_all)
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/*
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* flush_user_cache_all()
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*/
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ENTRY(arm940_flush_user_cache_all)
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/* FALLTHROUGH */
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/*
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* flush_kern_cache_all()
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*
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* Clean and invalidate the entire cache.
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*/
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ENTRY(arm940_flush_kern_cache_all)
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mov r2, #VM_EXEC
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/* FALLTHROUGH */
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/*
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* flush_user_cache_range(start, end, flags)
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*
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* There is no efficient way to flush a range of cache entries
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* in the specified address range. Thus, flushes all.
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*
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* - start - start address (inclusive)
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* - end - end address (exclusive)
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* - flags - vm_flags describing address space
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*/
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ENTRY(arm940_flush_user_cache_range)
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mov ip, #0
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, ip, c7, c6, 0 @ flush D cache
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#else
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 3 to 0
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#endif
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tst r2, #VM_EXEC
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mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcrne p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* coherent_kern_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_coherent_kern_range)
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/* FALLTHROUGH */
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/*
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* coherent_user_range(start, end)
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*
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* Ensure coherency between the Icache and the Dcache in the
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* region described by start, end. If you have non-snooping
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* Harvard caches, you need to implement this function.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_coherent_user_range)
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/* FALLTHROUGH */
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/*
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* flush_kern_dcache_area(void *addr, size_t size)
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*
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* Ensure no D cache aliasing occurs, either with itself or
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* the I cache
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*
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* - addr - kernel address
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* - size - region size
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*/
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ENTRY(arm940_flush_kern_dcache_area)
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_inv_range(start, end)
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*
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* There is no efficient way to invalidate a specifid virtual
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* address range. Thus, invalidates all.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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arm940_dma_inv_range:
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_clean_range(start, end)
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*
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* There is no efficient way to clean a specifid virtual
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* address range. Thus, cleans all.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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arm940_dma_clean_range:
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ENTRY(cpu_arm940_dcache_clean_area)
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mov ip, #0
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2: mcr p15, 0, r3, c7, c10, 2 @ clean D entry
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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#endif
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_flush_range(start, end)
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*
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* There is no efficient way to clean and invalidate a specifid
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* virtual address range.
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*
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* - start - virtual start address
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* - end - virtual end address
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*/
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ENTRY(arm940_dma_flush_range)
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mov ip, #0
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mov r1, #(CACHE_DSEGMENTS - 1) << 4 @ 4 segments
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1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
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2:
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#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
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mcr p15, 0, r3, c7, c14, 2 @ clean/flush D entry
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#else
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mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
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#endif
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subs r3, r3, #1 << 26
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bcs 2b @ entries 63 to 0
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subs r1, r1, #1 << 4
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bcs 1b @ segments 7 to 0
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mcr p15, 0, ip, c7, c10, 4 @ drain WB
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mov pc, lr
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/*
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* dma_map_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm940_dma_map_area)
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add r1, r1, r0
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cmp r2, #DMA_TO_DEVICE
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beq arm940_dma_clean_range
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bcs arm940_dma_inv_range
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b arm940_dma_flush_range
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ENDPROC(arm940_dma_map_area)
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/*
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* dma_unmap_area(start, size, dir)
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* - start - kernel virtual start address
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* - size - size of region
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* - dir - DMA direction
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*/
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ENTRY(arm940_dma_unmap_area)
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mov pc, lr
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ENDPROC(arm940_dma_unmap_area)
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ENTRY(arm940_cache_fns)
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.long arm940_flush_icache_all
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.long arm940_flush_kern_cache_all
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.long arm940_flush_user_cache_all
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.long arm940_flush_user_cache_range
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.long arm940_coherent_kern_range
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.long arm940_coherent_user_range
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.long arm940_flush_kern_dcache_area
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.long arm940_dma_map_area
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.long arm940_dma_unmap_area
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.long arm940_dma_flush_range
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__CPUINIT
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.type __arm940_setup, #function
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__arm940_setup:
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
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mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
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mcr p15, 0, r0, c7, c10, 4 @ drain WB
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mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
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mcr p15, 0, r0, c6, c4, 0
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mcr p15, 0, r0, c6, c5, 0
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mcr p15, 0, r0, c6, c6, 0
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mcr p15, 0, r0, c6, c7, 0
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mcr p15, 0, r0, c6, c3, 1 @ disable instruction area 3~7
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mcr p15, 0, r0, c6, c4, 1
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mcr p15, 0, r0, c6, c5, 1
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mcr p15, 0, r0, c6, c6, 1
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mcr p15, 0, r0, c6, c7, 1
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mov r0, #0x0000003F @ base = 0, size = 4GB
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mcr p15, 0, r0, c6, c0, 0 @ set area 0, default
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mcr p15, 0, r0, c6, c0, 1
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ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
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ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c1, 0 @ set area 1, RAM
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mcr p15, 0, r0, c6, c1, 1
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ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
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ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
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mov r2, #10 @ 11 is the minimum (4KB)
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1: add r2, r2, #1 @ area size *= 2
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mov r1, r1, lsr #1
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bne 1b @ count not zero r-shift
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orr r0, r0, r2, lsl #1 @ the area register value
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orr r0, r0, #1 @ set enable bit
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mcr p15, 0, r0, c6, c2, 0 @ set area 2, ROM/FLASH
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mcr p15, 0, r0, c6, c2, 1
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mov r0, #0x06
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mcr p15, 0, r0, c2, c0, 0 @ Region 1&2 cacheable
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mcr p15, 0, r0, c2, c0, 1
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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mov r0, #0x00 @ disable whole write buffer
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#else
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mov r0, #0x02 @ Region 1 write bufferred
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#endif
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mcr p15, 0, r0, c3, c0, 0
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mov r0, #0x10000
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sub r0, r0, #1 @ r0 = 0xffff
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mcr p15, 0, r0, c5, c0, 0 @ all read/write access
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mcr p15, 0, r0, c5, c0, 1
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mrc p15, 0, r0, c1, c0 @ get control register
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orr r0, r0, #0x00001000 @ I-cache
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orr r0, r0, #0x00000005 @ MPU/D-cache
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mov pc, lr
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.size __arm940_setup, . - __arm940_setup
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__INITDATA
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/*
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* Purpose : Function pointers used to access above functions - all calls
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* come through these
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*/
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.type arm940_processor_functions, #object
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ENTRY(arm940_processor_functions)
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.word nommu_early_abort
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.word legacy_pabort
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.word cpu_arm940_proc_init
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.word cpu_arm940_proc_fin
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.word cpu_arm940_reset
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.word cpu_arm940_do_idle
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.word cpu_arm940_dcache_clean_area
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.word cpu_arm940_switch_mm
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.word 0 @ cpu_*_set_pte
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.size arm940_processor_functions, . - arm940_processor_functions
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.section ".rodata"
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.type cpu_arch_name, #object
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cpu_arch_name:
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.asciz "armv4t"
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.size cpu_arch_name, . - cpu_arch_name
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.type cpu_elf_name, #object
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cpu_elf_name:
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.asciz "v4"
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.size cpu_elf_name, . - cpu_elf_name
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.type cpu_arm940_name, #object
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cpu_arm940_name:
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.ascii "ARM940T"
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.size cpu_arm940_name, . - cpu_arm940_name
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.align
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.section ".proc.info.init", #alloc, #execinstr
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.type __arm940_proc_info,#object
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__arm940_proc_info:
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.long 0x41009400
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.long 0xff00fff0
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.long 0
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b __arm940_setup
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.long cpu_arch_name
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.long cpu_elf_name
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.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
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.long cpu_arm940_name
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.long arm940_processor_functions
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.long 0
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.long 0
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.long arm940_cache_fns
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.size __arm940_proc_info, . - __arm940_proc_info
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