forked from luck/tmp_suning_uos_patched
8fac2f96ab
Pull ARM updates from Russell King:
"Low priority fixes and updates for ARM:
- add some missing includes
- efficiency improvements in system call entry code when tracing is
enabled
- ensure ARMv6+ is always built as EABI
- export save_stack_trace_tsk()
- fix fatal signal handling during mm fault
- build translation table base address register from scratch
- appropriately align the .data section to a word boundary where we
rely on that data being word aligned"
* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 8691/1: Export save_stack_trace_tsk()
ARM: 8692/1: mm: abort uaccess retries upon fatal signal
ARM: 8690/1: lpae: build TTB control register value from scratch in v7_ttb_setup
ARM: align .data section
ARM: always enable AEABI for ARMv6+
ARM: avoid saving and restoring registers unnecessarily
ARM: move PC value into r9
ARM: obtain thread info structure later
ARM: use aliases for registers in entry-common
ARM: 8689/1: scu: add missing errno include
ARM: 8688/1: pm: add missing types include
84 lines
2.1 KiB
ArmAsm
84 lines
2.1 KiB
ArmAsm
/*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#include <linux/serial_reg.h>
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/* External port on Zoom2/3 */
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#define ZOOM_UART_BASE 0x10000000
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#define ZOOM_UART_VIRT 0xfa400000
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#define OMAP_PORT_SHIFT 2
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#define ZOOM_PORT_SHIFT 1
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#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
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.pushsection .data
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.align 2
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omap_uart_phys: .word 0
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omap_uart_virt: .word 0
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omap_uart_lsr: .word 0
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.popsection
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.macro addruart, rp, rv, tmp
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/* Use omap_uart_phys/virt if already configured */
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10: adr \rp, 99f @ get effective addr of 99f
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ldr \rv, [\rp] @ get absolute addr of 99f
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sub \rv, \rv, \rp @ offset between the two
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ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
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sub \tmp, \rp, \rv @ make it effective
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ldr \rp, [\tmp, #0] @ omap_uart_phys
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ldr \rv, [\tmp, #4] @ omap_uart_virt
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cmp \rp, #0 @ is port configured?
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cmpne \rv, #0
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bne 100f @ already configured
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/* Configure the UART offset from the phys/virt base */
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#ifdef CONFIG_DEBUG_ZOOM_UART
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ldr \rp, =ZOOM_UART_BASE
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str \rp, [\tmp, #0] @ omap_uart_phys
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ldr \rp, =ZOOM_UART_VIRT
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str \rp, [\tmp, #4] @ omap_uart_virt
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mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
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str \rp, [\tmp, #8] @ omap_uart_lsr
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#endif
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b 10b
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.align
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99: .word .
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.word omap_uart_phys
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.ltorg
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100: /* Pass the UART_LSR reg address */
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ldr \tmp, [\tmp, #8] @ omap_uart_lsr
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add \rp, \rp, \tmp
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add \rv, \rv, \tmp
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.endm
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.macro senduart,rd,rx
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orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
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bic \rx, \rx, #0xff @ get base (THR) reg address
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strb \rd, [\rx] @ send lower byte of rd
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orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
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bic \rd, \rd, #(0xff << 24) @ restore original rd
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.endm
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.macro busyuart,rd,rx
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1001: ldrb \rd, [\rx] @ rx contains UART_LSR address
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and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
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teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
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bne 1001b
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.endm
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.macro waituart,rd,rx
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.endm
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