forked from luck/tmp_suning_uos_patched
148f9bb877
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
are flagged as __cpuinit -- so if we remove the __cpuinit from
arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
content into no-ops as early as possible, since that will get rid
of these warnings. In any case, they are temporary and harmless.
This removes all the arch/x86 uses of the __cpuinit macros from
all C files. x86 only had the one __CPUINIT used in assembly files,
and it wasn't paired off with a .previous or a __FINIT, so we can
delete it directly w/o any corresponding additional change there.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: x86@kernel.org
Acked-by: Ingo Molnar <mingo@kernel.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
265 lines
6.4 KiB
C
265 lines
6.4 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Numascale NumaConnect-Specific APIC Code
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*
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* Copyright (C) 2011 Numascale AS. All rights reserved.
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*
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* Send feedback to <support@numascale.com>
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*
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*/
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#include <linux/errno.h>
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#include <linux/threads.h>
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#include <linux/cpumask.h>
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#include <linux/string.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/ctype.h>
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#include <linux/init.h>
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#include <linux/hardirq.h>
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#include <linux/delay.h>
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#include <asm/numachip/numachip.h>
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#include <asm/numachip/numachip_csr.h>
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#include <asm/smp.h>
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#include <asm/apic.h>
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#include <asm/ipi.h>
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#include <asm/apic_flat_64.h>
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#include <asm/pgtable.h>
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static int numachip_system __read_mostly;
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static const struct apic apic_numachip __read_mostly;
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static unsigned int get_apic_id(unsigned long x)
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{
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unsigned long value;
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unsigned int id;
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rdmsrl(MSR_FAM10H_NODE_ID, value);
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id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U);
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return id;
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}
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static unsigned long set_apic_id(unsigned int id)
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{
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unsigned long x;
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x = ((id & 0xffU) << 24);
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return x;
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}
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static unsigned int read_xapic_id(void)
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{
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return get_apic_id(apic_read(APIC_ID));
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}
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static int numachip_apic_id_valid(int apicid)
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{
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/* Trust what bootloader passes in MADT */
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return 1;
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}
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static int numachip_apic_id_registered(void)
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{
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return physid_isset(read_xapic_id(), phys_cpu_present_map);
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}
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static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
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{
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return initial_apic_id >> index_msb;
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}
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static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
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{
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union numachip_csr_g3_ext_irq_gen int_gen;
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int_gen.s._destination_apic_id = phys_apicid;
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int_gen.s._vector = 0;
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int_gen.s._msgtype = APIC_DM_INIT >> 8;
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int_gen.s._index = 0;
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write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
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int_gen.s._msgtype = APIC_DM_STARTUP >> 8;
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int_gen.s._vector = start_rip >> 12;
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write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
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atomic_set(&init_deasserted, 1);
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return 0;
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}
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static void numachip_send_IPI_one(int cpu, int vector)
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{
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union numachip_csr_g3_ext_irq_gen int_gen;
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int apicid = per_cpu(x86_cpu_to_apicid, cpu);
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int_gen.s._destination_apic_id = apicid;
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int_gen.s._vector = vector;
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int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8;
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int_gen.s._index = 0;
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write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v);
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}
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static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
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{
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unsigned int cpu;
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for_each_cpu(cpu, mask)
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numachip_send_IPI_one(cpu, vector);
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}
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static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
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int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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for_each_cpu(cpu, mask) {
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if (cpu != this_cpu)
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numachip_send_IPI_one(cpu, vector);
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}
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}
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static void numachip_send_IPI_allbutself(int vector)
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{
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unsigned int this_cpu = smp_processor_id();
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unsigned int cpu;
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for_each_online_cpu(cpu) {
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if (cpu != this_cpu)
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numachip_send_IPI_one(cpu, vector);
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}
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}
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static void numachip_send_IPI_all(int vector)
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{
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numachip_send_IPI_mask(cpu_online_mask, vector);
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}
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static void numachip_send_IPI_self(int vector)
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{
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__default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL);
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}
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static int __init numachip_probe(void)
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{
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return apic == &apic_numachip;
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}
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static void __init map_csrs(void)
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{
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printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n",
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NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1);
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init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
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printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n",
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NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1);
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init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE);
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}
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static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
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{
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if (c->phys_proc_id != node) {
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c->phys_proc_id = node;
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per_cpu(cpu_llc_id, smp_processor_id()) = node;
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}
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}
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static int __init numachip_system_init(void)
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{
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unsigned int val;
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if (!numachip_system)
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return 0;
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x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
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x86_init.pci.arch_init = pci_numachip_init;
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map_csrs();
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val = read_lcsr(CSR_G0_NODE_IDS);
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printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val);
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return 0;
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}
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early_initcall(numachip_system_init);
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static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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if (!strncmp(oem_id, "NUMASC", 6)) {
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numachip_system = 1;
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return 1;
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}
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return 0;
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}
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static const struct apic apic_numachip __refconst = {
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.name = "NumaConnect system",
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.probe = numachip_probe,
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.acpi_madt_oem_check = numachip_acpi_madt_oem_check,
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.apic_id_valid = numachip_apic_id_valid,
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.apic_id_registered = numachip_apic_id_registered,
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.irq_delivery_mode = dest_Fixed,
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.irq_dest_mode = 0, /* physical */
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.target_cpus = online_target_cpus,
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.disable_esr = 0,
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.dest_logical = 0,
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.check_apicid_used = NULL,
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.check_apicid_present = NULL,
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.vector_allocation_domain = default_vector_allocation_domain,
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.init_apic_ldr = flat_init_apic_ldr,
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.ioapic_phys_id_map = NULL,
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.setup_apic_routing = NULL,
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.multi_timer_check = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = NULL,
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.setup_portio_remap = NULL,
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.check_phys_apicid_present = default_check_phys_apicid_present,
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.enable_apic_mode = NULL,
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.phys_pkg_id = numachip_phys_pkg_id,
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.mps_oem_check = NULL,
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.get_apic_id = get_apic_id,
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.set_apic_id = set_apic_id,
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.apic_id_mask = 0xffU << 24,
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.cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
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.send_IPI_mask = numachip_send_IPI_mask,
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.send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
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.send_IPI_allbutself = numachip_send_IPI_allbutself,
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.send_IPI_all = numachip_send_IPI_all,
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.send_IPI_self = numachip_send_IPI_self,
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.wakeup_secondary_cpu = numachip_wakeup_secondary,
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.trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW,
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.trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH,
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.wait_for_init_deassert = NULL,
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.smp_callin_clear_local_apic = NULL,
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.inquire_remote_apic = NULL, /* REMRD not supported */
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.read = native_apic_mem_read,
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.write = native_apic_mem_write,
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.eoi_write = native_apic_mem_write,
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.icr_read = native_apic_icr_read,
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.icr_write = native_apic_icr_write,
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.wait_icr_idle = native_apic_wait_icr_idle,
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.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
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};
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apic_driver(apic_numachip);
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