forked from luck/tmp_suning_uos_patched
8d9ee21e98
For imx50-weim and imx6q-weim type of devices, there might a WEIM CS space configuration register in General Purpose Register controller, e.g. IOMUXC_GPR1 on i.MX6Q. Depending on which configuration of the following 4 is chosen for given system, IOMUXC_GPR1[11:0] should be set up as 05, 033, 0113 or 01111 correspondingly. CS0(128M) CS1(0M) CS2(0M) CS3(0M) CS0(64M) CS1(64M) CS2(0M) CS3(0M) CS0(64M) CS1(32M) CS2(32M) CS3(0M) CS0(32M) CS1(32M) CS2(32M) CS3(32M) The patch creates a function for such type of devices, which scans 'ranges' property of WEIM node and build the GPR value incrementally. Thus the WEIM CS GPR can be set up automatically at boot time. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Philippe De Muyter <phdm@macqel.be> Tested-by: Philippe De Muyter <phdm@macqel.be>
83 lines
2.9 KiB
Plaintext
83 lines
2.9 KiB
Plaintext
Device tree bindings for i.MX Wireless External Interface Module (WEIM)
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The term "wireless" does not imply that the WEIM is literally an interface
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without wires. It simply means that this module was originally designed for
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wireless and mobile applications that use low-power technology.
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The actual devices are instantiated from the child nodes of a WEIM node.
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Required properties:
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- compatible: Should contain one of the following:
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"fsl,imx1-weim"
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"fsl,imx27-weim"
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"fsl,imx51-weim"
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"fsl,imx50-weim"
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"fsl,imx6q-weim"
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- reg: A resource specifier for the register space
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(see the example below)
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- clocks: the clock, see the example below.
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- #address-cells: Must be set to 2 to allow memory address translation
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- #size-cells: Must be set to 1 to allow CS address passing
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- ranges: Must be set up to reflect the memory layout with four
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integer values for each chip-select line in use:
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<cs-number> 0 <physical address of mapping> <size>
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Optional properties:
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- fsl,weim-cs-gpr: For "fsl,imx50-weim" and "fsl,imx6q-weim" type of
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devices, it should be the phandle to the system General
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Purpose Register controller that contains WEIM CS GPR
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register, e.g. IOMUXC_GPR1 on i.MX6Q. IOMUXC_GPR1[11:0]
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should be set up as one of the following 4 possible
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values depending on the CS space configuration.
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IOMUXC_GPR1[11:0] CS0 CS1 CS2 CS3
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---------------------------------------------
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05 128M 0M 0M 0M
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033 64M 64M 0M 0M
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0113 64M 32M 32M 0M
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01111 32M 32M 32M 32M
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In case that the property is absent, the reset value or
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what bootloader sets up in IOMUXC_GPR1[11:0] will be
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used.
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Timing property for child nodes. It is mandatory, not optional.
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- fsl,weim-cs-timing: The timing array, contains timing values for the
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child node. We can get the CS index from the child
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node's "reg" property. The number of registers depends
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on the selected chip.
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For i.MX1, i.MX21 ("fsl,imx1-weim") there are two
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registers: CSxU, CSxL.
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For i.MX25, i.MX27, i.MX31 and i.MX35 ("fsl,imx27-weim")
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there are three registers: CSCRxU, CSCRxL, CSCRxA.
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For i.MX50, i.MX53 ("fsl,imx50-weim"),
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i.MX51 ("fsl,imx51-weim") and i.MX6Q ("fsl,imx6q-weim")
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there are six registers: CSxGCR1, CSxGCR2, CSxRCR1,
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CSxRCR2, CSxWCR1, CSxWCR2.
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Example for an imx6q-sabreauto board, the NOR flash connected to the WEIM:
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weim: weim@021b8000 {
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compatible = "fsl,imx6q-weim";
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reg = <0x021b8000 0x4000>;
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clocks = <&clks 196>;
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x08000000 0x08000000>;
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fsl,weim-cs-gpr = <&gpr>;
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nor@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x02000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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bank-width = <2>;
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fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
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0x0000c000 0x1404a38e 0x00000000>;
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};
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};
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