Heiko Stuebner 5035981979 clk-divider: make sure read-only dividers do not write to their register ... Commit e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") removed the special ops struct for read-only clocks and instead opted to handle them inside the regular ops. On the rk3368 this results in breakage as aclkm now gets set a value. While it is the same divider value, the A53 core still doesn't like it, which can result in the cpu ending up in a hang. The reason being that "ACLKENMasserts one clock cycle before the rising edge of ACLKM" and the clock should only be touched when STANDBYWFIL2 is asserted. To fix this, reintroduce the read-only ops but do include the round_rate callback. That way no writes that may be unsafe are done to the divider register in any case. The Rockchip use of the clk_divider_ops is adapted to this split again, as is the nxp, lpc18xx-ccu driver that was included since the original commit. On lpc18xx-ccu the divider seems to always be read-only so only uses the new ops now. Fixes: e6d5e7d90b ("clk-divider: Fix READ_ONLY when divider > 1") Reported-by: Zhang Qing <zhangqing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>		2016-01-29 12:44:37 -08:00
..
clk-cpu.c	clk: rockchip: allow more than 2 parents for cpuclk	2015-12-09 22:30:42 +01:00
clk-inverter.c	clk: Convert __clk_get_name(hw->clk) to clk_hw_get_name(hw)	2015-08-24 16:49:12 -07:00
clk-mmc-phase.c	The majority of the changes are driver updates and new device	2015-11-05 12:59:36 -08:00
clk-pll.c	clk: rockchip: add new pll-type for rk3036 and similar socs	2015-11-23 21:55:07 +01:00
clk-rk3036.c	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
clk-rk3188.c	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
clk-rk3228.c	clk: rockchip: only enter pll slow-mode directly before reboots on rk3288	2015-12-21 02:01:19 +01:00
clk-rk3288.c	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
clk-rk3368.c	clk: rockchip: only enter pll slow-mode directly before reboots on rk3288	2015-12-21 02:01:19 +01:00
clk-rockchip.c
clk.c	clk-divider: make sure read-only dividers do not write to their register	2016-01-29 12:44:37 -08:00
clk.h	Merge branch 'clk-rockchip' into clk-next	2016-01-02 13:41:09 -08:00
Makefile	clk: rockchip: add clock controller for rk3228	2015-12-12 20:04:54 +01:00
softrst.c