forked from luck/tmp_suning_uos_patched
9d0412680e
Now that Linux includes support for the Atmel AT91SAM9260 and AT91SAM9261 processors in addition to the original Atmel AT91RM9200 (with support for more AT91 processors pending), the "mach-at91rm9200" and "arch-at91rm9200" directories should be renamed to indicate their more generic nature. The following git commands should be run BEFORE applying this patch: git-mv arch/arm/mach-at91rm9200 arch/arm/mach-at91 git-mv include/asm-arm/arch-at91rm9200 include/asm-arm/arch-at91 Signed-off-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
54 lines
2.5 KiB
C
54 lines
2.5 KiB
C
/*
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* include/asm-arm/arch-at91/at91_aic.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Advanced Interrupt Controller (AIC) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91_AIC_H
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#define AT91_AIC_H
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#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
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#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
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#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
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#define AT91_AIC_SRCTYPE_LOW (0 << 5)
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#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
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#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
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#define AT91_AIC_SRCTYPE_RISING (3 << 5)
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#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
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#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
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#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
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#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
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#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
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#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
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#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
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#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
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#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
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#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
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#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
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#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
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#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
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#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
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#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
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#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
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#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
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#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
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#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
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#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
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#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
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#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
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#endif
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