forked from luck/tmp_suning_uos_patched
475be4d85a
isdn source code uses a not-current coding style. Update the coding style used on a per-line basis so that git diff -w shows only elided blank lines at EOF. Done with emacs and some scripts and some typing. Built x86 allyesconfig. No detected change in objdump -d or size. Signed-off-by: Joe Perches <joe@perches.com>
120 lines
4.4 KiB
C
120 lines
4.4 KiB
C
/* $Id: bkm_ax.h,v 1.5.6.3 2001/09/23 22:24:46 kai Exp $
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*
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* low level decls for T-Berkom cards A4T and Scitel Quadro (4*S0, passive)
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*
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* Author Roland Klabunde
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* Copyright by Roland Klabunde <R.Klabunde@Berkom.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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#ifndef __BKM_AX_H__
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#define __BKM_AX_H__
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/* Supported boards (subtypes) */
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#define SCT_1 1
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#define SCT_2 2
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#define SCT_3 3
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#define SCT_4 4
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#define BKM_A4T 5
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#define PLX_ADDR_PLX 0x14 /* Addr PLX configuration */
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#define PLX_ADDR_ISAC 0x18 /* Addr ISAC */
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#define PLX_ADDR_HSCX 0x1C /* Addr HSCX */
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#define PLX_ADDR_ALE 0x20 /* Addr ALE */
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#define PLX_ADDR_ALEPLUS 0x24 /* Next Addr behind ALE */
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#define PLX_SUBVEN 0x2C /* Offset SubVendor */
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#define PLX_SUBSYS 0x2E /* Offset SubSystem */
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/* Application specific registers I20 (Siemens SZB6120H) */
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typedef struct {
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/* Video front end horizontal configuration register */
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volatile u_int i20VFEHorzCfg; /* Offset 00 */
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/* Video front end vertical configuration register */
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volatile u_int i20VFEVertCfg; /* Offset 04 */
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/* Video front end scaler and pixel format register */
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volatile u_int i20VFEScaler; /* Offset 08 */
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/* Video display top register */
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volatile u_int i20VDispTop; /* Offset 0C */
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/* Video display bottom register */
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volatile u_int i20VDispBottom; /* Offset 10 */
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/* Video stride, status and frame grab register */
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volatile u_int i20VidFrameGrab;/* Offset 14 */
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/* Video display configuration register */
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volatile u_int i20VDispCfg; /* Offset 18 */
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/* Video masking map top */
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volatile u_int i20VMaskTop; /* Offset 1C */
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/* Video masking map bottom */
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volatile u_int i20VMaskBottom; /* Offset 20 */
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/* Overlay control register */
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volatile u_int i20OvlyControl; /* Offset 24 */
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/* System, PCI and general purpose pins control register */
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volatile u_int i20SysControl; /* Offset 28 */
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#define sysRESET 0x01000000 /* bit 24:Softreset (Low) */
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/* GPIO 4...0: Output fixed for our cfg! */
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#define sysCFG 0x000000E0 /* GPIO 7,6,5: Input */
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/* General purpose pins and guest bus control register */
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volatile u_int i20GuestControl;/* Offset 2C */
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#define guestWAIT_CFG 0x00005555 /* 4 PCI waits for all */
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#define guestISDN_INT_E 0x01000000 /* ISDN Int en (low) */
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#define guestVID_INT_E 0x02000000 /* Video interrupt en (low) */
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#define guestADI1_INT_R 0x04000000 /* ADI #1 int req (low) */
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#define guestADI2_INT_R 0x08000000 /* ADI #2 int req (low) */
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#define guestISDN_RES 0x10000000 /* ISDN reset bit (high) */
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#define guestADI1_INT_S 0x20000000 /* ADI #1 int pending (low) */
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#define guestADI2_INT_S 0x40000000 /* ADI #2 int pending (low) */
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#define guestISDN_INT_S 0x80000000 /* ISAC int pending (low) */
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#define g_A4T_JADE_RES 0x01000000 /* JADE Reset (High) */
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#define g_A4T_ISAR_RES 0x02000000 /* ISAR Reset (High) */
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#define g_A4T_ISAC_RES 0x04000000 /* ISAC Reset (High) */
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#define g_A4T_JADE_BOOTR 0x08000000 /* JADE enable boot SRAM (Low) NOT USED */
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#define g_A4T_ISAR_BOOTR 0x10000000 /* ISAR enable boot SRAM (Low) NOT USED */
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#define g_A4T_JADE_INT_S 0x20000000 /* JADE interrupt pnd (Low) */
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#define g_A4T_ISAR_INT_S 0x40000000 /* ISAR interrupt pnd (Low) */
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#define g_A4T_ISAC_INT_S 0x80000000 /* ISAC interrupt pnd (Low) */
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volatile u_int i20CodeSource; /* Offset 30 */
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volatile u_int i20CodeXferCtrl;/* Offset 34 */
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volatile u_int i20CodeMemPtr; /* Offset 38 */
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volatile u_int i20IntStatus; /* Offset 3C */
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volatile u_int i20IntCtrl; /* Offset 40 */
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#define intISDN 0x40000000 /* GIRQ1En (ISAC/ADI) (High) */
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#define intVID 0x20000000 /* GIRQ0En (VSYNC) (High) */
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#define intCOD 0x10000000 /* CodRepIrqEn (High) */
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#define intPCI 0x01000000 /* PCI IntA enable (High) */
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volatile u_int i20I2CCtrl; /* Offset 44 */
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} I20_REGISTER_FILE, *PI20_REGISTER_FILE;
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/*
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* Postoffice structure for A4T
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*
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*/
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#define PO_OFFSET 0x00000200 /* Postoffice offset from base */
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#define GCS_0 0x00000000 /* Guest bus chip selects */
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#define GCS_1 0x00100000
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#define GCS_2 0x00200000
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#define GCS_3 0x00300000
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#define PO_READ 0x00000000 /* R/W from/to guest bus */
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#define PO_WRITE 0x00800000
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#define PO_PEND 0x02000000
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#define POSTOFFICE(postoffice) *(volatile unsigned int *)(postoffice)
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/* Wait unlimited (don't worry) */
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#define __WAITI20__(postoffice) \
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do { \
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while ((POSTOFFICE(postoffice) & PO_PEND)) ; \
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} while (0)
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#endif /* __BKM_AX_H__ */
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