Will Deacon db6f41063c arm64: mm: don't treat user cache maintenance faults as writes ... On arm64, cache maintenance faults appear as data aborts with the CM bit set in the ESR. The WnR bit, usually used to distinguish between faulting loads and stores, always reads as 1 and (slightly confusingly) the instructions are treated as reads by the architecture. This patch fixes our fault handling code to treat cache maintenance faults in the same way as loads. Signed-off-by: Will Deacon <will.deacon@arm.com> Cc: <stable@vger.kernel.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>		2013-07-19 15:49:44 +01:00
..
cache.S	arm64: mm: Fix operands of clz in __flush_dcache_all	2013-05-14 15:44:50 +01:00
context.c
copypage.c
dma-mapping.c	arm64: Call swiotlb_init() instead of swiotlb_init_with_default_size()	2012-10-08 16:02:09 +01:00
extable.c
fault.c	arm64: mm: don't treat user cache maintenance faults as writes	2013-07-19 15:49:44 +01:00
flush.c	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
hugetlbpage.c	ARM64: mm: HugeTLB support.	2013-06-14 09:52:40 +01:00
init.c	mm/microblaze: prepare for removing num_physpages and simplify mem_init()	2013-07-03 16:07:36 -07:00
ioremap.c
Makefile	ARM64: mm: HugeTLB support.	2013-06-14 09:52:40 +01:00
mm.h	arm64: Remove __flush_dcache_page()	2013-06-07 17:58:30 +01:00
mmap.c	mm: remove free_area_cache	2013-07-10 18:11:34 -07:00
mmu.c	Merge branch 'for-next/hugepages' of git://git.linaro.org/people/stevecapper/linux into upstream-hugepages	2013-07-01 11:20:58 +01:00
pgd.c
proc-macros.S
proc.S	arm64: debug: clear mdscr_el1 instead of taking the OS lock	2013-05-13 11:44:56 +01:00
tlb.S