forked from luck/tmp_suning_uos_patched
ffd58bd2e4
This patch extends the kirkwood's PCIe support up to 2 controllers as in the 6282 devices. Signed-off-by: Saeed Bishara <saeed@marvell.com> Signed-off-by: Nicolas Pitre <nico@fluxnic.net>
140 lines
3.5 KiB
C
140 lines
3.5 KiB
C
/*
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* arch/arm/mach-kirkwood/openrd-setup.c
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*
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* Marvell OpenRD (Base|Client|Ultimate) Board Setup
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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#include <linux/ata_platform.h>
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#include <linux/mv643xx_eth.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <mach/kirkwood.h>
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#include <plat/mvsdio.h>
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#include "common.h"
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#include "mpp.h"
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static struct mtd_partition openrd_nand_parts[] = {
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{
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.name = "u-boot",
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.offset = 0,
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.size = SZ_1M,
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.mask_flags = MTD_WRITEABLE
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}, {
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.name = "uImage",
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.offset = MTDPART_OFS_NXTBLK,
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.size = SZ_4M
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}, {
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.name = "root",
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.offset = MTDPART_OFS_NXTBLK,
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.size = MTDPART_SIZ_FULL
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},
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};
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static struct mv643xx_eth_platform_data openrd_ge00_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(8),
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};
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static struct mv643xx_eth_platform_data openrd_ge01_data = {
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.phy_addr = MV643XX_ETH_PHY_ADDR(24),
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};
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static struct mv_sata_platform_data openrd_sata_data = {
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.n_ports = 2,
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};
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static struct mvsdio_platform_data openrd_mvsdio_data = {
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.gpio_card_detect = 29, /* MPP29 used as SD card detect */
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};
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static unsigned int openrd_mpp_config[] __initdata = {
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MPP29_GPIO,
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0
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};
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static void __init openrd_init(void)
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{
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/*
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* Basic setup. Needs to be called early.
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*/
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kirkwood_init();
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kirkwood_mpp_conf(openrd_mpp_config);
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kirkwood_uart0_init();
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kirkwood_nand_init(ARRAY_AND_SIZE(openrd_nand_parts), 25);
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kirkwood_ehci_init();
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if (machine_is_openrd_ultimate()) {
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openrd_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
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openrd_ge01_data.phy_addr = MV643XX_ETH_PHY_ADDR(1);
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}
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kirkwood_ge00_init(&openrd_ge00_data);
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if (!machine_is_openrd_base())
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kirkwood_ge01_init(&openrd_ge01_data);
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kirkwood_sata_init(&openrd_sata_data);
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kirkwood_sdio_init(&openrd_mvsdio_data);
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kirkwood_i2c_init();
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}
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static int __init openrd_pci_init(void)
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{
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if (machine_is_openrd_base() ||
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machine_is_openrd_client() ||
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machine_is_openrd_ultimate())
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kirkwood_pcie_init(KW_PCIE0);
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return 0;
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}
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subsys_initcall(openrd_pci_init);
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#ifdef CONFIG_MACH_OPENRD_BASE
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MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
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/* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
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.phys_io = KIRKWOOD_REGS_PHYS_BASE,
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.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.init_machine = openrd_init,
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.map_io = kirkwood_map_io,
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.init_irq = kirkwood_init_irq,
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.timer = &kirkwood_timer,
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MACHINE_END
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#endif
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#ifdef CONFIG_MACH_OPENRD_CLIENT
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MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
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/* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
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.phys_io = KIRKWOOD_REGS_PHYS_BASE,
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.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.init_machine = openrd_init,
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.map_io = kirkwood_map_io,
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.init_irq = kirkwood_init_irq,
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.timer = &kirkwood_timer,
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MACHINE_END
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#endif
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#ifdef CONFIG_MACH_OPENRD_ULTIMATE
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MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
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/* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
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.phys_io = KIRKWOOD_REGS_PHYS_BASE,
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.io_pg_offst = ((KIRKWOOD_REGS_VIRT_BASE) >> 18) & 0xfffc,
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.boot_params = 0x00000100,
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.init_machine = openrd_init,
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.map_io = kirkwood_map_io,
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.init_irq = kirkwood_init_irq,
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.timer = &kirkwood_timer,
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MACHINE_END
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#endif
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