forked from luck/tmp_suning_uos_patched
6e7f8b8e47
For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6132/
28 lines
725 B
C
28 lines
725 B
C
#ifndef __ASM_TLB_H
|
|
#define __ASM_TLB_H
|
|
|
|
/*
|
|
* MIPS doesn't need any special per-pte or per-vma handling, except
|
|
* we need to flush cache for area to be unmapped.
|
|
*/
|
|
#define tlb_start_vma(tlb, vma) \
|
|
do { \
|
|
if (!tlb->fullmm) \
|
|
flush_cache_range(vma, vma->vm_start, vma->vm_end); \
|
|
} while (0)
|
|
#define tlb_end_vma(tlb, vma) do { } while (0)
|
|
#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
|
|
|
|
/*
|
|
* .. because we flush the whole mm when it fills up.
|
|
*/
|
|
#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
|
|
|
|
#define UNIQUE_ENTRYHI(idx) \
|
|
((CKSEG0 + ((idx) << (PAGE_SHIFT + 1))) | \
|
|
(cpu_has_tlbinv ? MIPS_ENTRYHI_EHINV : 0))
|
|
|
|
#include <asm-generic/tlb.h>
|
|
|
|
#endif /* __ASM_TLB_H */
|