Petar Jovanovic 846fbcfe6f MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1 ... Define Cavium Octeon as a CPU that has support for mips32r1, mips32r2 and mips64r1. This will affect show_cpuinfo() that will now correctly expose mips32r1, mips32r2 and mips64r1 as supported ISAs. Signed-off-by: Petar Jovanovic <petar.jovanovic@rt-rk.com> Reviewed-by: Maciej W. Rozycki <macro@imgtec.com> Acked-by: David Daney <david.daney@cavium.com> Cc: petar.jovanovic@imgtec.com Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15749/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2017-08-29 15:21:52 +02:00
..
asm	MIPS: Octeon: Expose support for mips32r1, mips32r2 and mips64r1	2017-08-29 15:21:52 +02:00
uapi/asm	tty: Fix TIOCGPTPEER ioctl definition	2017-07-17 17:04:41 +02:00