Chen-Yu Tsai 13e0dde8b2 clk: sunxi-ng: Support multiple variable pre-dividers ... On the A83T, the AHB1 clock has a shared pre-divider on the two PLL-PERIPH clock parents. To support such instances of shared pre-dividers, this patch extends the mux clock type to support multiple variable pre-dividers. As the pre-dividers are only used to calculate the rate, but do not participate in the factorization process, this is fairly straightforward. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>		2017-06-07 15:32:15 +02:00
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at91
axis
axs10x
bcm
berlin
h8300
hisilicon
imx
ingenic
keystone
loongson1
mediatek
meson
microchip
mmp
mvebu
mxs
nxp
pistachio
pxa
qcom
renesas
rockchip
samsung
sirf
socfpga
spear
st
sunxi
sunxi-ng	clk: sunxi-ng: Support multiple variable pre-dividers	2017-06-07 15:32:15 +02:00
tegra
ti
uniphier
ux500
versatile
x86
zte
zynq
clk-asm9260.c
clk-axi-clkgen.c
clk-axm5516.c
clk-cdce706.c
clk-cdce925.c
clk-clps711x.c
clk-composite.c
clk-conf.c
clk-cs2000-cp.c
clk-devres.c
clk-divider.c	clk: divider: Make divider_round_rate take the parent clock	2017-06-07 15:32:12 +02:00
clk-efm32gg.c
clk-fixed-factor.c
clk-fixed-rate.c
clk-fractional-divider.c
clk-gate.c
clk-gpio.c
clk-hi655x.c
clk-highbank.c
clk-max77686.c
clk-mb86s7x.c
clk-moxart.c
clk-multiplier.c
clk-mux.c
clk-nomadik.c
clk-nspire.c
clk-oxnas.c
clk-palmas.c
clk-pwm.c
clk-qoriq.c
clk-rk808.c
clk-s2mps11.c
clk-scpi.c
clk-si514.c
clk-si570.c
clk-si5351.c
clk-si5351.h
clk-stm32f4.c
clk-tango4.c
clk-twl6040.c
clk-u300.c
clk-versaclock5.c
clk-vt8500.c
clk-wm831x.c
clk-xgene.c
clk.c
clk.h
clkdev.c
Kconfig
Makefile