forked from luck/tmp_suning_uos_patched
37b7a97884
This takes a bit of a sledgehammer to the machvec I/O routines. The iomem case requires no special casing and so can just be dropped outright. This only leaves the ioport casing for PCI and SuperIO mangling. With the SuperIO case going through the standard ioport mapping, it's possible to replace everything with generic routines. With this done the standard I/O routines are tidied up and NO_IOPORT now gets default-enabled for the vast majority of boards. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
432 lines
10 KiB
C
432 lines
10 KiB
C
/*
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* New-style PCI core.
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*
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* Copyright (c) 2004 - 2009 Paul Mundt
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* Copyright (c) 2002 M. R. Brown
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*
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* Modelled after arch/mips/pci/pci.c:
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* Copyright (C) 2003, 04 Ralf Baechle (ralf@linux-mips.org)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/dma-debug.h>
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#include <linux/io.h>
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#include <linux/mutex.h>
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#include <linux/spinlock.h>
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unsigned long PCIBIOS_MIN_IO = 0x0000;
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unsigned long PCIBIOS_MIN_MEM = 0;
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/*
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* The PCI controller list.
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*/
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static struct pci_channel *hose_head, **hose_tail = &hose_head;
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static int pci_initialized;
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static void __devinit pcibios_scanbus(struct pci_channel *hose)
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{
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static int next_busno;
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static int need_domain_info;
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struct pci_bus *bus;
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bus = pci_scan_bus(next_busno, hose->pci_ops, hose);
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hose->bus = bus;
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need_domain_info = need_domain_info || hose->index;
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hose->need_domain_info = need_domain_info;
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if (bus) {
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next_busno = bus->subordinate + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224) {
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next_busno = 0;
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need_domain_info = 1;
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}
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pci_bus_size_bridges(bus);
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pci_bus_assign_resources(bus);
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pci_enable_bridges(bus);
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}
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}
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/*
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* This interrupt-safe spinlock protects all accesses to PCI
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* configuration space.
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*/
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DEFINE_RAW_SPINLOCK(pci_config_lock);
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static DEFINE_MUTEX(pci_scan_mutex);
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int __devinit register_pci_controller(struct pci_channel *hose)
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{
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int i;
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for (i = 0; i < hose->nr_resources; i++) {
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struct resource *res = hose->resources + i;
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if (res->flags & IORESOURCE_IO) {
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if (request_resource(&ioport_resource, res) < 0)
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goto out;
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} else {
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if (request_resource(&iomem_resource, res) < 0)
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goto out;
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}
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}
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*hose_tail = hose;
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hose_tail = &hose->next;
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/*
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* Do not panic here but later - this might hapen before console init.
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*/
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if (!hose->io_map_base) {
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printk(KERN_WARNING
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"registering PCI controller with io_map_base unset\n");
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}
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/*
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* Setup the ERR/PERR and SERR timers, if available.
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*/
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pcibios_enable_timers(hose);
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/*
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* Scan the bus if it is register after the PCI subsystem
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* initialization.
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*/
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if (pci_initialized) {
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mutex_lock(&pci_scan_mutex);
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pcibios_scanbus(hose);
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mutex_unlock(&pci_scan_mutex);
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}
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return 0;
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out:
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for (--i; i >= 0; i--)
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release_resource(&hose->resources[i]);
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printk(KERN_WARNING "Skipping PCI bus scan due to resource conflict\n");
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return -1;
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}
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static int __init pcibios_init(void)
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{
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struct pci_channel *hose;
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/* Scan all of the recorded PCI controllers. */
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for (hose = hose_head; hose; hose = hose->next)
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pcibios_scanbus(hose);
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pci_fixup_irqs(pci_common_swizzle, pcibios_map_platform_irq);
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dma_debug_add_bus(&pci_bus_type);
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pci_initialized = 1;
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return 0;
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}
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subsys_initcall(pcibios_init);
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static void pcibios_fixup_device_resources(struct pci_dev *dev,
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struct pci_bus *bus)
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{
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/* Update device resources. */
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struct pci_channel *hose = bus->sysdata;
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unsigned long offset = 0;
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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if (!dev->resource[i].start)
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continue;
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if (dev->resource[i].flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (dev->resource[i].flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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dev->resource[i].start += offset;
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dev->resource[i].end += offset;
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}
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}
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/*
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* Called after each bus is probed, but before its children
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* are examined.
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*/
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void __devinit pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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struct list_head *ln;
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struct pci_channel *hose = bus->sysdata;
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if (!dev) {
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int i;
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for (i = 0; i < hose->nr_resources; i++)
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bus->resource[i] = hose->resources + i;
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}
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for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
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dev = pci_dev_b(ln);
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if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
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pcibios_fixup_device_resources(dev, bus);
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}
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}
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/*
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* We need to avoid collisions with `mirrored' VGA ports
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* and other strange ISA hardware, so we always want the
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* addresses to be allocated in the 0x000-0x0ff region
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* modulo 0x400.
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*/
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resource_size_t pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_channel *hose = dev->sysdata;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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if (start < PCIBIOS_MIN_IO + hose->resources[0].start)
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start = PCIBIOS_MIN_IO + hose->resources[0].start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400.
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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}
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return start;
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}
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void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_channel *hose = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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struct pci_channel *hose = dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_offset;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_offset;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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int pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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return pci_enable_resources(dev, mask);
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}
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/*
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* If we set up a device for bus mastering, we need to check and set
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* the latency timer as it may not be properly set.
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*/
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static unsigned int pcibios_max_latency = 255;
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_INFO "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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void __init pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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char * __devinit __weak pcibios_setup(char *str)
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{
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return str;
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}
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static void __init
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pcibios_bus_report_status_early(struct pci_channel *hose,
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int top_bus, int current_bus,
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unsigned int status_mask, int warn)
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{
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unsigned int pci_devfn;
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u16 status;
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int ret;
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for (pci_devfn = 0; pci_devfn < 0xff; pci_devfn++) {
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if (PCI_FUNC(pci_devfn))
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continue;
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ret = early_read_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_STATUS, &status);
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if (ret != PCIBIOS_SUCCESSFUL)
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continue;
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if (status == 0xffff)
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continue;
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early_write_config_word(hose, top_bus, current_bus,
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pci_devfn, PCI_STATUS,
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status & status_mask);
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if (warn)
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printk("(%02x:%02x: %04X) ", current_bus,
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pci_devfn, status);
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}
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}
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/*
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* We can't use pci_find_device() here since we are
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* called from interrupt context.
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*/
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static void __init_refok
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pcibios_bus_report_status(struct pci_bus *bus, unsigned int status_mask,
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int warn)
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{
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struct pci_dev *dev;
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list_for_each_entry(dev, &bus->devices, bus_list) {
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u16 status;
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/*
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* ignore host bridge - we handle
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* that separately
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*/
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if (dev->bus->number == 0 && dev->devfn == 0)
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continue;
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pci_read_config_word(dev, PCI_STATUS, &status);
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if (status == 0xffff)
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continue;
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if ((status & status_mask) == 0)
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continue;
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/* clear the status errors */
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pci_write_config_word(dev, PCI_STATUS, status & status_mask);
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if (warn)
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printk("(%s: %04X) ", pci_name(dev), status);
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}
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list_for_each_entry(dev, &bus->devices, bus_list)
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if (dev->subordinate)
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pcibios_bus_report_status(dev->subordinate, status_mask, warn);
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}
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void __init_refok pcibios_report_status(unsigned int status_mask, int warn)
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{
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struct pci_channel *hose;
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for (hose = hose_head; hose; hose = hose->next) {
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if (unlikely(!hose->bus))
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pcibios_bus_report_status_early(hose, hose_head->index,
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hose->index, status_mask, warn);
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else
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pcibios_bus_report_status(hose->bus, status_mask, warn);
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}
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}
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int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
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enum pci_mmap_state mmap_state, int write_combine)
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{
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/*
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* I/O space can be accessed via normal processor loads and stores on
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* this platform but for now we elect not to do this and portable
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* drivers should not do this anyway.
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*/
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if (mmap_state == pci_mmap_io)
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return -EINVAL;
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/*
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* Ignore write-combine; for now only return uncached mappings.
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*/
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vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
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return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
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vma->vm_end - vma->vm_start,
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vma->vm_page_prot);
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}
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#ifndef CONFIG_GENERIC_IOMAP
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static void __iomem *ioport_map_pci(struct pci_dev *dev,
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unsigned long port, unsigned int nr)
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{
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struct pci_channel *chan = dev->sysdata;
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if (unlikely(!chan->io_map_base)) {
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chan->io_map_base = sh_io_port_base;
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if (pci_domains_supported)
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panic("To avoid data corruption io_map_base MUST be "
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"set with multiple PCI domains.");
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}
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return (void __iomem *)(chan->io_map_base + port);
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}
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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unsigned long flags = pci_resource_flags(dev, bar);
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if (unlikely(!len || !start))
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map_pci(dev, start, len);
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if (flags & IORESOURCE_MEM) {
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if (flags & IORESOURCE_CACHEABLE)
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return ioremap(start, len);
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return ioremap_nocache(start, len);
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}
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return NULL;
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}
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EXPORT_SYMBOL(pci_iomap);
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void pci_iounmap(struct pci_dev *dev, void __iomem *addr)
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{
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iounmap);
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#endif /* CONFIG_GENERIC_IOMAP */
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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EXPORT_SYMBOL(PCIBIOS_MIN_IO);
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EXPORT_SYMBOL(PCIBIOS_MIN_MEM);
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#endif
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