forked from luck/tmp_suning_uos_patched
f50b153b19
To add support for 36-bit physical addressing on e500 the following changes have been made. The changes are generalized to support any physical address size larger than 32-bits: * Allow FSL Book-E parts to use a 64-bit PTE, it is 44-bits of pfn, 20-bits of flags. * Introduced new CPU feature (CPU_FTR_BIG_PHYS) to allow runtime handling of updating hardware register (SPRN_MAS7) which holds the upper 32-bits of physical address that will be written into the TLB. This is useful since not all e500 cores support 36-bit physical addressing. * Currently have a pass through implementation of fixup_bigphys_addr * Moved _PAGE_DIRTY in the 64-bit PTE case to free room for three additional storage attributes that may exist in future FSL Book-E cores and updated fault handler to copy these bits into the hardware TLBs. Signed-off-by: Kumar Gala <kumar.gala@freescale.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
/*
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* include/asm-ppc/cputable.h
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*
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* Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef __ASM_PPC_CPUTABLE_H
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#define __ASM_PPC_CPUTABLE_H
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/* Exposed to userland CPU features */
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#define PPC_FEATURE_32 0x80000000
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#define PPC_FEATURE_64 0x40000000
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#define PPC_FEATURE_601_INSTR 0x20000000
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#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
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#define PPC_FEATURE_HAS_FPU 0x08000000
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#define PPC_FEATURE_HAS_MMU 0x04000000
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#define PPC_FEATURE_HAS_4xxMAC 0x02000000
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#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
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#define PPC_FEATURE_HAS_SPE 0x00800000
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#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
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#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
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#ifdef __KERNEL__
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#ifndef __ASSEMBLY__
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/* This structure can grow, it's real size is used by head.S code
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* via the mkdefs mecanism.
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*/
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struct cpu_spec;
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typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
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struct cpu_spec {
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/* CPU is matched via (PVR & pvr_mask) == pvr_value */
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unsigned int pvr_mask;
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unsigned int pvr_value;
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char *cpu_name;
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unsigned int cpu_features; /* Kernel features */
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unsigned int cpu_user_features; /* Userland features */
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/* cache line sizes */
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unsigned int icache_bsize;
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unsigned int dcache_bsize;
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/* number of performance monitor counters */
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unsigned int num_pmcs;
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/* this is called to initialize various CPU bits like L1 cache,
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* BHT, SPD, etc... from head.S before branching to identify_machine
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*/
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cpu_setup_t cpu_setup;
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};
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extern struct cpu_spec cpu_specs[];
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extern struct cpu_spec *cur_cpu_spec[];
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static inline unsigned int cpu_has_feature(unsigned int feature)
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{
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return cur_cpu_spec[0]->cpu_features & feature;
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}
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#endif /* __ASSEMBLY__ */
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/* CPU kernel features */
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#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
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#define CPU_FTR_L2CR 0x00000002
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#define CPU_FTR_SPEC7450 0x00000004
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#define CPU_FTR_ALTIVEC 0x00000008
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#define CPU_FTR_TAU 0x00000010
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#define CPU_FTR_CAN_DOZE 0x00000020
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#define CPU_FTR_USE_TB 0x00000040
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#define CPU_FTR_604_PERF_MON 0x00000080
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#define CPU_FTR_601 0x00000100
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#define CPU_FTR_HPTE_TABLE 0x00000200
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#define CPU_FTR_CAN_NAP 0x00000400
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#define CPU_FTR_L3CR 0x00000800
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#define CPU_FTR_L3_DISABLE_NAP 0x00001000
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#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
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#define CPU_FTR_DUAL_PLL_750FX 0x00004000
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#define CPU_FTR_NO_DPM 0x00008000
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#define CPU_FTR_HAS_HIGH_BATS 0x00010000
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#define CPU_FTR_NEED_COHERENT 0x00020000
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#define CPU_FTR_NO_BTIC 0x00040000
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#define CPU_FTR_BIG_PHYS 0x00080000
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#ifdef __ASSEMBLY__
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#define BEGIN_FTR_SECTION 98:
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#define END_FTR_SECTION(msk, val) \
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99: \
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.section __ftr_fixup,"a"; \
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.align 2; \
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.long msk; \
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.long val; \
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.long 98b; \
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.long 99b; \
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.previous
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#else
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#define BEGIN_FTR_SECTION "98:\n"
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#define END_FTR_SECTION(msk, val) \
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"99:\n" \
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" .section __ftr_fixup,\"a\";\n" \
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" .align 2;\n" \
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" .long "#msk";\n" \
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" .long "#val";\n" \
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" .long 98b;\n" \
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" .long 99b;\n" \
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" .previous\n"
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#endif /* __ASSEMBLY__ */
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#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
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#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
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#endif /* __ASM_PPC_CPUTABLE_H */
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#endif /* __KERNEL__ */
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