forked from luck/tmp_suning_uos_patched
1626aeb881
The intention of using port_mask in SFF init helpers was to eventually support exoctic configurations such as combination of legacy and native port on the same controller. This never became actually necessary and the related code always has been subtly broken one way or the other. Now that new init model is in place, there is no reason to make common helpers capable of handling all corner cases. Exotic cases can simply dealt within LLDs as necessary. This patch removes port_mask handling in SFF init helpers. SFF init helpers don't take n_ports argument and interpret it into port_mask anymore. All information is carried via port_info. n_ports argument is dropped and always two ports are allocated. LLD can tell SFF to skip certain port by marking it dummy. Note that SFF code has been treating unuvailable ports this way for a long time until recent breakage fix from Linus and is consistent with how other drivers handle with unavailable ports. This fixes 1-port legacy host handling still broken after the recent native mode fix and simplifies SFF init logic. The following changes are made... * ata_pci_init_native_host() and ata_init_legacy_host() both now try to initialized whatever they can and mark failed ports dummy. They return 0 if any port is successfully initialized. * ata_pci_prepare_native_host() and ata_pci_init_one() now doesn't take n_ports argument. All info should be specified via port_info array. Always two ports are allocated. * ata_pci_init_bmdma() exported to be used by LLDs in exotic cases. * port_info handling in all LLDs are standardized - all port_info arrays are const stack variable named ppi. Unless the second port is different from the first, its port_info is specified as NULL (tells libata that it's identical to the last non-NULL port_info). * pata_hpt37x/hpt3x2n: don't modify static variable directly. Make an on-stack copy instead as ata_piix does. * pata_uli: It has 4 ports instead of 2. Don't use ata_pci_prepare_native_host(). Allocate the host explicitly and use init helpers. It's simple enough. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
357 lines
9.2 KiB
C
357 lines
9.2 KiB
C
/*
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* pata_efar.c - EFAR PIIX clone controller driver
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*
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* (C) 2005 Red Hat <alan@redhat.com>
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*
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* Some parts based on ata_piix.c by Jeff Garzik and others.
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*
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* The EFAR is a PIIX4 clone with UDMA66 support. Unlike the later
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* Intel ICH controllers the EFAR widened the UDMA mode register bits
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* and doesn't require the funky clock selection.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/blkdev.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <scsi/scsi_host.h>
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#include <linux/libata.h>
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#include <linux/ata.h>
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#define DRV_NAME "pata_efar"
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#define DRV_VERSION "0.4.4"
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/**
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* efar_pre_reset - Enable bits
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* @ap: Port
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* @deadline: deadline jiffies for the operation
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*
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* Perform cable detection for the EFAR ATA interface. This is
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* different to the PIIX arrangement
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*/
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static int efar_pre_reset(struct ata_port *ap, unsigned long deadline)
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{
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static const struct pci_bits efar_enable_bits[] = {
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{ 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
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{ 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
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};
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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if (!pci_test_config_bits(pdev, &efar_enable_bits[ap->port_no]))
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return -ENOENT;
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return ata_std_prereset(ap, deadline);
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}
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/**
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* efar_probe_reset - Probe specified port on PATA host controller
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* @ap: Port to probe
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void efar_error_handler(struct ata_port *ap)
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{
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ata_bmdma_drive_eh(ap, efar_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
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}
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/**
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* efar_cable_detect - check for 40/80 pin
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* @ap: Port
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*
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* Perform cable detection for the EFAR ATA interface. This is
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* different to the PIIX arrangement
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*/
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static int efar_cable_detect(struct ata_port *ap)
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{
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struct pci_dev *pdev = to_pci_dev(ap->host->dev);
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u8 tmp;
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pci_read_config_byte(pdev, 0x47, &tmp);
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if (tmp & (2 >> ap->port_no))
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return ATA_CBL_PATA40;
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return ATA_CBL_PATA80;
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}
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/**
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* efar_set_piomode - Initialize host controller PATA PIO timings
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* @ap: Port whose timings we are configuring
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* @adev: um
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*
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* Set PIO mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev)
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{
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unsigned int pio = adev->pio_mode - XFER_PIO_0;
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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unsigned int idetm_port= ap->port_no ? 0x42 : 0x40;
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u16 idetm_data;
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int control = 0;
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/*
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* See Intel Document 298600-004 for the timing programing rules
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* for PIIX/ICH. The EFAR is a clone so very similar
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*/
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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if (pio > 2)
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control |= 1; /* TIME1 enable */
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if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */
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control |= 2; /* IE enable */
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/* Intel specifies that the PPE functionality is for disk only */
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if (adev->class == ATA_DEV_ATA)
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control |= 4; /* PPE enable */
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pci_read_config_word(dev, idetm_port, &idetm_data);
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/* Enable PPE, IE and TIME as appropriate */
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if (adev->devno == 0) {
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idetm_data &= 0xCCF0;
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idetm_data |= control;
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idetm_data |= (timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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} else {
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int shift = 4 * ap->port_no;
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u8 slave_data;
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idetm_data &= 0xCC0F;
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idetm_data |= (control << 4);
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/* Slave timing in seperate register */
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pci_read_config_byte(dev, 0x44, &slave_data);
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slave_data &= 0x0F << shift;
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << shift;
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pci_write_config_byte(dev, 0x44, slave_data);
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}
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idetm_data |= 0x4000; /* Ensure SITRE is enabled */
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pci_write_config_word(dev, idetm_port, idetm_data);
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}
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/**
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* efar_set_dmamode - Initialize host controller PATA DMA timings
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* @ap: Port whose timings we are configuring
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* @adev: Device to program
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*
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* Set UDMA/MWDMA mode for device, in host controller PCI config space.
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*
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* LOCKING:
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* None (inherited from caller).
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*/
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static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev)
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{
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struct pci_dev *dev = to_pci_dev(ap->host->dev);
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u8 master_port = ap->port_no ? 0x42 : 0x40;
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u16 master_data;
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u8 speed = adev->dma_mode;
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int devid = adev->devno + 2 * ap->port_no;
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u8 udma_enable;
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static const /* ISP RTC */
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u8 timings[][2] = { { 0, 0 },
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{ 0, 0 },
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{ 1, 0 },
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{ 2, 1 },
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{ 2, 3 }, };
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pci_read_config_word(dev, master_port, &master_data);
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pci_read_config_byte(dev, 0x48, &udma_enable);
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if (speed >= XFER_UDMA_0) {
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unsigned int udma = adev->dma_mode - XFER_UDMA_0;
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u16 udma_timing;
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udma_enable |= (1 << devid);
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/* Load the UDMA mode number */
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pci_read_config_word(dev, 0x4A, &udma_timing);
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udma_timing &= ~(7 << (4 * devid));
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udma_timing |= udma << (4 * devid);
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pci_write_config_word(dev, 0x4A, udma_timing);
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} else {
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/*
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* MWDMA is driven by the PIO timings. We must also enable
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* IORDY unconditionally along with TIME1. PPE has already
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* been set when the PIO timing was set.
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*/
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unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0;
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unsigned int control;
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u8 slave_data;
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const unsigned int needed_pio[3] = {
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XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
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};
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int pio = needed_pio[mwdma] - XFER_PIO_0;
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control = 3; /* IORDY|TIME1 */
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/* If the drive MWDMA is faster than it can do PIO then
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we must force PIO into PIO0 */
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if (adev->pio_mode < needed_pio[mwdma])
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/* Enable DMA timing only */
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control |= 8; /* PIO cycles in PIO0 */
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if (adev->devno) { /* Slave */
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master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */
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master_data |= control << 4;
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pci_read_config_byte(dev, 0x44, &slave_data);
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slave_data &= (0x0F + 0xE1 * ap->port_no);
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/* Load the matching timing */
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slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0);
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pci_write_config_byte(dev, 0x44, slave_data);
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} else { /* Master */
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master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY
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and master timing bits */
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master_data |= control;
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master_data |=
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(timings[pio][0] << 12) |
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(timings[pio][1] << 8);
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}
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udma_enable &= ~(1 << devid);
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pci_write_config_word(dev, master_port, master_data);
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}
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pci_write_config_byte(dev, 0x48, udma_enable);
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}
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static struct scsi_host_template efar_sht = {
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.module = THIS_MODULE,
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.name = DRV_NAME,
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.ioctl = ata_scsi_ioctl,
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.queuecommand = ata_scsi_queuecmd,
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.can_queue = ATA_DEF_QUEUE,
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.this_id = ATA_SHT_THIS_ID,
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.sg_tablesize = LIBATA_MAX_PRD,
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.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
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.emulated = ATA_SHT_EMULATED,
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.use_clustering = ATA_SHT_USE_CLUSTERING,
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.proc_name = DRV_NAME,
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.dma_boundary = ATA_DMA_BOUNDARY,
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.slave_configure = ata_scsi_slave_config,
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.slave_destroy = ata_scsi_slave_destroy,
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.bios_param = ata_std_bios_param,
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};
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static const struct ata_port_operations efar_ops = {
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.port_disable = ata_port_disable,
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.set_piomode = efar_set_piomode,
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.set_dmamode = efar_set_dmamode,
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.mode_filter = ata_pci_default_filter,
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.tf_load = ata_tf_load,
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.tf_read = ata_tf_read,
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.check_status = ata_check_status,
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.exec_command = ata_exec_command,
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.dev_select = ata_std_dev_select,
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.freeze = ata_bmdma_freeze,
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.thaw = ata_bmdma_thaw,
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.error_handler = efar_error_handler,
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.post_internal_cmd = ata_bmdma_post_internal_cmd,
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.cable_detect = efar_cable_detect,
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.bmdma_setup = ata_bmdma_setup,
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.bmdma_start = ata_bmdma_start,
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.bmdma_stop = ata_bmdma_stop,
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.bmdma_status = ata_bmdma_status,
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.qc_prep = ata_qc_prep,
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.qc_issue = ata_qc_issue_prot,
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.data_xfer = ata_data_xfer,
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.irq_handler = ata_interrupt,
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.irq_clear = ata_bmdma_irq_clear,
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.irq_on = ata_irq_on,
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.irq_ack = ata_irq_ack,
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.port_start = ata_port_start,
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};
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/**
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* efar_init_one - Register EFAR ATA PCI device with kernel services
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* @pdev: PCI device to register
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* @ent: Entry in efar_pci_tbl matching with @pdev
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*
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* Called from kernel PCI layer.
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*
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* LOCKING:
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* Inherited from PCI layer (may sleep).
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*
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* RETURNS:
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* Zero on success, or -ERRNO value.
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*/
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static int efar_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
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{
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static int printed_version;
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static const struct ata_port_info info = {
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.sht = &efar_sht,
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.flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma1-2 */
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.udma_mask = 0x0f, /* UDMA 66 */
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.port_ops = &efar_ops,
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};
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const struct ata_port_info *ppi[] = { &info, NULL };
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if (!printed_version++)
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dev_printk(KERN_DEBUG, &pdev->dev,
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"version " DRV_VERSION "\n");
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return ata_pci_init_one(pdev, ppi);
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}
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static const struct pci_device_id efar_pci_tbl[] = {
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{ PCI_VDEVICE(EFAR, 0x9130), },
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{ } /* terminate list */
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};
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static struct pci_driver efar_pci_driver = {
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.name = DRV_NAME,
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.id_table = efar_pci_tbl,
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.probe = efar_init_one,
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.remove = ata_pci_remove_one,
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#ifdef CONFIG_PM
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.suspend = ata_pci_device_suspend,
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.resume = ata_pci_device_resume,
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#endif
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};
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static int __init efar_init(void)
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{
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return pci_register_driver(&efar_pci_driver);
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}
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static void __exit efar_exit(void)
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{
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pci_unregister_driver(&efar_pci_driver);
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}
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module_init(efar_init);
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module_exit(efar_exit);
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MODULE_AUTHOR("Alan Cox");
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MODULE_DESCRIPTION("SCSI low-level driver for EFAR PIIX clones");
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MODULE_LICENSE("GPL");
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MODULE_DEVICE_TABLE(pci, efar_pci_tbl);
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MODULE_VERSION(DRV_VERSION);
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