forked from luck/tmp_suning_uos_patched
f3e16ccd03
Read the number of MPIC interrupts from the controller and only register that many. [gregory.clement@free-electrons.com: rename armada symbol name to fit with new name: armada_370_xp] Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Lior Amsalem <alior@marvell.com>
134 lines
3.4 KiB
C
134 lines
3.4 KiB
C
/*
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* Marvell Armada 370 and Armada XP SoC IRQ handling
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*
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* Copyright (C) 2012 Marvell
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*
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* Lior Amsalem <alior@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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* Ben Dooks <ben.dooks@codethink.co.uk>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/irqdomain.h>
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#include <asm/mach/arch.h>
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#include <asm/exception.h>
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/* Interrupt Controller Registers Map */
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#define ARMADA_370_XP_INT_SET_MASK_OFFS (0x48)
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#define ARMADA_370_XP_INT_CLEAR_MASK_OFFS (0x4C)
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#define ARMADA_370_XP_INT_CONTROL (0x00)
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#define ARMADA_370_XP_INT_SET_ENABLE_OFFS (0x30)
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#define ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS (0x34)
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#define ARMADA_370_XP_CPU_INTACK_OFFS (0x44)
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static void __iomem *per_cpu_int_base;
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static void __iomem *main_int_base;
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static struct irq_domain *armada_370_xp_mpic_domain;
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static void armada_370_xp_irq_mask(struct irq_data *d)
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{
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writel(irqd_to_hwirq(d),
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per_cpu_int_base + ARMADA_370_XP_INT_SET_MASK_OFFS);
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}
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static void armada_370_xp_irq_unmask(struct irq_data *d)
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{
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writel(irqd_to_hwirq(d),
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per_cpu_int_base + ARMADA_370_XP_INT_CLEAR_MASK_OFFS);
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}
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static struct irq_chip armada_370_xp_irq_chip = {
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.name = "armada_370_xp_irq",
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.irq_mask = armada_370_xp_irq_mask,
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.irq_mask_ack = armada_370_xp_irq_mask,
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.irq_unmask = armada_370_xp_irq_unmask,
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};
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static int armada_370_xp_mpic_irq_map(struct irq_domain *h,
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unsigned int virq, irq_hw_number_t hw)
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{
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armada_370_xp_irq_mask(irq_get_irq_data(virq));
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writel(hw, main_int_base + ARMADA_370_XP_INT_SET_ENABLE_OFFS);
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irq_set_chip_and_handler(virq, &armada_370_xp_irq_chip,
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handle_level_irq);
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irq_set_status_flags(virq, IRQ_LEVEL);
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set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
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return 0;
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}
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static struct irq_domain_ops armada_370_xp_mpic_irq_ops = {
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.map = armada_370_xp_mpic_irq_map,
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.xlate = irq_domain_xlate_onecell,
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};
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static int __init armada_370_xp_mpic_of_init(struct device_node *node,
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struct device_node *parent)
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{
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u32 control;
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main_int_base = of_iomap(node, 0);
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per_cpu_int_base = of_iomap(node, 1);
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BUG_ON(!main_int_base);
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BUG_ON(!per_cpu_int_base);
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control = readl(main_int_base + ARMADA_370_XP_INT_CONTROL);
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armada_370_xp_mpic_domain =
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irq_domain_add_linear(node, (control >> 2) & 0x3ff,
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&armada_370_xp_mpic_irq_ops, NULL);
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if (!armada_370_xp_mpic_domain)
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panic("Unable to add Armada_370_Xp MPIC irq domain (DT)\n");
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irq_set_default_host(armada_370_xp_mpic_domain);
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return 0;
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}
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asmlinkage void __exception_irq_entry armada_370_xp_handle_irq(struct pt_regs
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*regs)
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{
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u32 irqstat, irqnr;
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do {
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irqstat = readl_relaxed(per_cpu_int_base +
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ARMADA_370_XP_CPU_INTACK_OFFS);
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irqnr = irqstat & 0x3FF;
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if (irqnr < 1023) {
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irqnr =
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irq_find_mapping(armada_370_xp_mpic_domain, irqnr);
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handle_IRQ(irqnr, regs);
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continue;
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}
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break;
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} while (1);
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}
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static const struct of_device_id mpic_of_match[] __initconst = {
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{.compatible = "marvell,mpic", .data = armada_370_xp_mpic_of_init},
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{},
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};
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void __init armada_370_xp_init_irq(void)
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{
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of_irq_init(mpic_of_match);
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}
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