forked from luck/tmp_suning_uos_patched
3c603573d2
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de>
Link: https://lore.kernel.org/r/20200713114719.33839-1-grandmaster@al2klimov.de
Signed-off-by: Jonathan Corbet <corbet@lwn.net>
243 lines
7.7 KiB
ReStructuredText
243 lines
7.7 KiB
ReStructuredText
.. SPDX-License-Identifier: GPL-2.0
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==========
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Nested VMX
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==========
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Overview
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---------
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On Intel processors, KVM uses Intel's VMX (Virtual-Machine eXtensions)
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to easily and efficiently run guest operating systems. Normally, these guests
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*cannot* themselves be hypervisors running their own guests, because in VMX,
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guests cannot use VMX instructions.
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The "Nested VMX" feature adds this missing capability - of running guest
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hypervisors (which use VMX) with their own nested guests. It does so by
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allowing a guest to use VMX instructions, and correctly and efficiently
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emulating them using the single level of VMX available in the hardware.
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We describe in much greater detail the theory behind the nested VMX feature,
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its implementation and its performance characteristics, in the OSDI 2010 paper
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"The Turtles Project: Design and Implementation of Nested Virtualization",
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available at:
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https://www.usenix.org/events/osdi10/tech/full_papers/Ben-Yehuda.pdf
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Terminology
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-----------
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Single-level virtualization has two levels - the host (KVM) and the guests.
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In nested virtualization, we have three levels: The host (KVM), which we call
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L0, the guest hypervisor, which we call L1, and its nested guest, which we
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call L2.
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Running nested VMX
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------------------
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The nested VMX feature is disabled by default. It can be enabled by giving
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the "nested=1" option to the kvm-intel module.
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No modifications are required to user space (qemu). However, qemu's default
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emulated CPU type (qemu64) does not list the "VMX" CPU feature, so it must be
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explicitly enabled, by giving qemu one of the following options:
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- cpu host (emulated CPU has all features of the real CPU)
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- cpu qemu64,+vmx (add just the vmx feature to a named CPU type)
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ABIs
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----
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Nested VMX aims to present a standard and (eventually) fully-functional VMX
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implementation for the a guest hypervisor to use. As such, the official
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specification of the ABI that it provides is Intel's VMX specification,
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namely volume 3B of their "Intel 64 and IA-32 Architectures Software
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Developer's Manual". Not all of VMX's features are currently fully supported,
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but the goal is to eventually support them all, starting with the VMX features
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which are used in practice by popular hypervisors (KVM and others).
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As a VMX implementation, nested VMX presents a VMCS structure to L1.
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As mandated by the spec, other than the two fields revision_id and abort,
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this structure is *opaque* to its user, who is not supposed to know or care
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about its internal structure. Rather, the structure is accessed through the
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VMREAD and VMWRITE instructions.
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Still, for debugging purposes, KVM developers might be interested to know the
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internals of this structure; This is struct vmcs12 from arch/x86/kvm/vmx.c.
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The name "vmcs12" refers to the VMCS that L1 builds for L2. In the code we
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also have "vmcs01", the VMCS that L0 built for L1, and "vmcs02" is the VMCS
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which L0 builds to actually run L2 - how this is done is explained in the
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aforementioned paper.
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For convenience, we repeat the content of struct vmcs12 here. If the internals
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of this structure changes, this can break live migration across KVM versions.
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VMCS12_REVISION (from vmx.c) should be changed if struct vmcs12 or its inner
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struct shadow_vmcs is ever changed.
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::
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typedef u64 natural_width;
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struct __packed vmcs12 {
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/* According to the Intel spec, a VMCS region must start with
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* these two user-visible fields */
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u32 revision_id;
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u32 abort;
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u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
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u32 padding[7]; /* room for future expansion */
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u64 io_bitmap_a;
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u64 io_bitmap_b;
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u64 msr_bitmap;
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u64 vm_exit_msr_store_addr;
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u64 vm_exit_msr_load_addr;
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u64 vm_entry_msr_load_addr;
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u64 tsc_offset;
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u64 virtual_apic_page_addr;
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u64 apic_access_addr;
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u64 ept_pointer;
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u64 guest_physical_address;
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u64 vmcs_link_pointer;
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u64 guest_ia32_debugctl;
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u64 guest_ia32_pat;
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u64 guest_ia32_efer;
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u64 guest_pdptr0;
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u64 guest_pdptr1;
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u64 guest_pdptr2;
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u64 guest_pdptr3;
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u64 host_ia32_pat;
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u64 host_ia32_efer;
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u64 padding64[8]; /* room for future expansion */
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natural_width cr0_guest_host_mask;
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natural_width cr4_guest_host_mask;
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natural_width cr0_read_shadow;
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natural_width cr4_read_shadow;
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natural_width dead_space[4]; /* Last remnants of cr3_target_value[0-3]. */
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natural_width exit_qualification;
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natural_width guest_linear_address;
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natural_width guest_cr0;
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natural_width guest_cr3;
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natural_width guest_cr4;
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natural_width guest_es_base;
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natural_width guest_cs_base;
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natural_width guest_ss_base;
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natural_width guest_ds_base;
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natural_width guest_fs_base;
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natural_width guest_gs_base;
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natural_width guest_ldtr_base;
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natural_width guest_tr_base;
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natural_width guest_gdtr_base;
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natural_width guest_idtr_base;
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natural_width guest_dr7;
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natural_width guest_rsp;
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natural_width guest_rip;
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natural_width guest_rflags;
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natural_width guest_pending_dbg_exceptions;
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natural_width guest_sysenter_esp;
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natural_width guest_sysenter_eip;
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natural_width host_cr0;
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natural_width host_cr3;
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natural_width host_cr4;
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natural_width host_fs_base;
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natural_width host_gs_base;
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natural_width host_tr_base;
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natural_width host_gdtr_base;
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natural_width host_idtr_base;
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natural_width host_ia32_sysenter_esp;
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natural_width host_ia32_sysenter_eip;
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natural_width host_rsp;
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natural_width host_rip;
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natural_width paddingl[8]; /* room for future expansion */
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u32 pin_based_vm_exec_control;
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u32 cpu_based_vm_exec_control;
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u32 exception_bitmap;
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u32 page_fault_error_code_mask;
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u32 page_fault_error_code_match;
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u32 cr3_target_count;
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u32 vm_exit_controls;
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u32 vm_exit_msr_store_count;
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u32 vm_exit_msr_load_count;
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u32 vm_entry_controls;
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u32 vm_entry_msr_load_count;
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u32 vm_entry_intr_info_field;
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u32 vm_entry_exception_error_code;
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u32 vm_entry_instruction_len;
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u32 tpr_threshold;
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u32 secondary_vm_exec_control;
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u32 vm_instruction_error;
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u32 vm_exit_reason;
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u32 vm_exit_intr_info;
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u32 vm_exit_intr_error_code;
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u32 idt_vectoring_info_field;
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u32 idt_vectoring_error_code;
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u32 vm_exit_instruction_len;
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u32 vmx_instruction_info;
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u32 guest_es_limit;
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u32 guest_cs_limit;
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u32 guest_ss_limit;
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u32 guest_ds_limit;
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u32 guest_fs_limit;
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u32 guest_gs_limit;
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u32 guest_ldtr_limit;
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u32 guest_tr_limit;
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u32 guest_gdtr_limit;
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u32 guest_idtr_limit;
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u32 guest_es_ar_bytes;
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u32 guest_cs_ar_bytes;
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u32 guest_ss_ar_bytes;
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u32 guest_ds_ar_bytes;
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u32 guest_fs_ar_bytes;
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u32 guest_gs_ar_bytes;
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u32 guest_ldtr_ar_bytes;
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u32 guest_tr_ar_bytes;
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u32 guest_interruptibility_info;
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u32 guest_activity_state;
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u32 guest_sysenter_cs;
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u32 host_ia32_sysenter_cs;
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u32 padding32[8]; /* room for future expansion */
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u16 virtual_processor_id;
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u16 guest_es_selector;
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u16 guest_cs_selector;
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u16 guest_ss_selector;
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u16 guest_ds_selector;
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u16 guest_fs_selector;
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u16 guest_gs_selector;
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u16 guest_ldtr_selector;
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u16 guest_tr_selector;
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u16 host_es_selector;
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u16 host_cs_selector;
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u16 host_ss_selector;
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u16 host_ds_selector;
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u16 host_fs_selector;
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u16 host_gs_selector;
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u16 host_tr_selector;
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};
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Authors
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-------
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These patches were written by:
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- Abel Gordon, abelg <at> il.ibm.com
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- Nadav Har'El, nyh <at> il.ibm.com
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- Orit Wasserman, oritw <at> il.ibm.com
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- Ben-Ami Yassor, benami <at> il.ibm.com
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- Muli Ben-Yehuda, muli <at> il.ibm.com
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With contributions by:
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- Anthony Liguori, aliguori <at> us.ibm.com
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- Mike Day, mdday <at> us.ibm.com
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- Michael Factor, factor <at> il.ibm.com
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- Zvi Dubitzky, dubi <at> il.ibm.com
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And valuable reviews by:
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- Avi Kivity, avi <at> redhat.com
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- Gleb Natapov, gleb <at> redhat.com
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- Marcelo Tosatti, mtosatti <at> redhat.com
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- Kevin Tian, kevin.tian <at> intel.com
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- and others.
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