forked from luck/tmp_suning_uos_patched
1d9ef3ecd7
Also many plat_timer_setup() can be killed too. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
140 lines
3.8 KiB
C
140 lines
3.8 KiB
C
#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <asm/i8253.h>
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#include <asm/sni.h>
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#include <asm/time.h>
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#include <asm-generic/rtc.h>
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#define SNI_CLOCK_TICK_RATE 3686400
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#define SNI_COUNTER2_DIV 64
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#define SNI_COUNTER0_DIV ((SNI_CLOCK_TICK_RATE / SNI_COUNTER2_DIV) / HZ)
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static void sni_a20r_timer_ack(void)
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{
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*(volatile u8 *)A20R_PT_TIM0_ACK = 0x0; wmb();
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}
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/*
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* a20r platform uses 2 counters to divide the input frequency.
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* Counter 2 output is connected to Counter 0 & 1 input.
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*/
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static void __init sni_a20r_timer_setup(struct irqaction *irq)
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{
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*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0x34; wmb();
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*(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV) & 0xff; wmb();
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*(volatile u8 *)(A20R_PT_CLOCK_BASE + 0) = (SNI_COUNTER0_DIV >> 8) & 0xff; wmb();
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*(volatile u8 *)(A20R_PT_CLOCK_BASE + 12) = 0xb4; wmb();
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*(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV) & 0xff; wmb();
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*(volatile u8 *)(A20R_PT_CLOCK_BASE + 8) = (SNI_COUNTER2_DIV >> 8) & 0xff; wmb();
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setup_irq(SNI_A20R_IRQ_TIMER, irq);
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mips_timer_ack = sni_a20r_timer_ack;
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}
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#define SNI_8254_TICK_RATE 1193182UL
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#define SNI_8254_TCSAMP_COUNTER ((SNI_8254_TICK_RATE / HZ) + 255)
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static __init unsigned long dosample(void)
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{
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u32 ct0, ct1;
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volatile u8 msb, lsb;
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/* Start the counter. */
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outb_p(0x34, 0x43);
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outb_p(SNI_8254_TCSAMP_COUNTER & 0xff, 0x40);
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outb(SNI_8254_TCSAMP_COUNTER >> 8, 0x40);
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/* Get initial counter invariant */
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ct0 = read_c0_count();
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/* Latch and spin until top byte of counter0 is zero */
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do {
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outb(0x00, 0x43);
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lsb = inb(0x40);
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msb = inb(0x40);
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ct1 = read_c0_count();
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} while (msb);
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/* Stop the counter. */
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outb(0x38, 0x43);
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/*
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* Return the difference, this is how far the r4k counter increments
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* for every 1/HZ seconds. We round off the nearest 1 MHz of master
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* clock (= 1000000 / HZ / 2).
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*/
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/*return (ct1 - ct0 + (500000/HZ/2)) / (500000/HZ) * (500000/HZ);*/
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return (ct1 - ct0) / (500000/HZ) * (500000/HZ);
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}
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/*
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* Here we need to calibrate the cycle counter to at least be close.
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*/
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void __init plat_time_init(void)
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{
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unsigned long r4k_ticks[3];
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unsigned long r4k_tick;
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/*
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* Figure out the r4k offset, the algorithm is very simple and works in
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* _all_ cases as long as the 8254 counter register itself works ok (as
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* an interrupt driving timer it does not because of bug, this is why
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* we are using the onchip r4k counter/compare register to serve this
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* purpose, but for r4k_offset calculation it will work ok for us).
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* There are other very complicated ways of performing this calculation
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* but this one works just fine so I am not going to futz around. ;-)
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*/
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printk(KERN_INFO "Calibrating system timer... ");
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dosample(); /* Prime cache. */
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dosample(); /* Prime cache. */
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/* Zero is NOT an option. */
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do {
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r4k_ticks[0] = dosample();
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} while (!r4k_ticks[0]);
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do {
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r4k_ticks[1] = dosample();
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} while (!r4k_ticks[1]);
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if (r4k_ticks[0] != r4k_ticks[1]) {
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printk("warning: timer counts differ, retrying... ");
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r4k_ticks[2] = dosample();
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if (r4k_ticks[2] == r4k_ticks[0]
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|| r4k_ticks[2] == r4k_ticks[1])
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r4k_tick = r4k_ticks[2];
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else {
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printk("disagreement, using average... ");
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r4k_tick = (r4k_ticks[0] + r4k_ticks[1]
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+ r4k_ticks[2]) / 3;
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}
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} else
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r4k_tick = r4k_ticks[0];
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printk("%d [%d.%04d MHz CPU]\n", (int) r4k_tick,
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(int) (r4k_tick / (500000 / HZ)),
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(int) (r4k_tick % (500000 / HZ)));
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mips_hpt_frequency = r4k_tick * HZ;
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setup_pit_timer();
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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switch (sni_brd_type) {
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case SNI_BRD_10:
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case SNI_BRD_10NEW:
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case SNI_BRD_TOWER_OASIC:
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case SNI_BRD_MINITOWER:
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sni_a20r_timer_setup(irq);
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break;
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}
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}
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unsigned long read_persistent_clock(void)
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{
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return -1;
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}
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