forked from luck/tmp_suning_uos_patched
180 lines
6.2 KiB
C
180 lines
6.2 KiB
C
/*
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* The following devices are accessable using this driver using
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* GPIO_MAJOR (120) and a couple of minor numbers.
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*
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* For ETRAX 100LX (CONFIG_ETRAX_ARCH_V10):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 8 bit GPIO, each bit can change direction
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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* /dev/gpiog minor 3
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* g0dir, g8_15dir, g16_23dir, g24 dir configurable in R_GEN_CONFIG
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* g1-g7 and g25-g31 is both input and outputs but on different pins
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* Also note that some bits change pins depending on what interfaces
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* are enabled.
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*
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* For ETRAX FS (CONFIG_ETRAXFS):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
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* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
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* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
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* /dev/gpioe minor 5, 18 bit GPIO, each bit can change direction
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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*
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* For ARTPEC-3 (CONFIG_CRIS_MACH_ARTPEC3):
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* /dev/gpioa minor 0, 8 bit GPIO, each bit can change direction
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* /dev/gpiob minor 1, 18 bit GPIO, each bit can change direction
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* /dev/gpioc minor 3, 18 bit GPIO, each bit can change direction
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* /dev/gpiod minor 4, 18 bit GPIO, each bit can change direction
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* /dev/leds minor 2, Access to leds depending on kernelconfig
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* /dev/pwm0 minor 16, PWM channel 0 on PA30
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* /dev/pwm1 minor 17, PWM channel 1 on PA31
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* /dev/pwm2 minor 18, PWM channel 2 on PB26
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*
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*/
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#ifndef _ASM_ETRAXGPIO_H
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#define _ASM_ETRAXGPIO_H
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/* etraxgpio _IOC_TYPE, bits 8 to 15 in ioctl cmd */
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#ifdef CONFIG_ETRAX_ARCH_V10
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_G 3
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#define GPIO_MINOR_LAST 3
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#endif
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#ifdef CONFIG_ETRAXFS
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_C 3
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#define GPIO_MINOR_D 4
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#define GPIO_MINOR_E 5
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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#define GPIO_MINOR_V 6
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#define GPIO_MINOR_LAST 6
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#else
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#define GPIO_MINOR_LAST 5
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#endif
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#endif
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#ifdef CONFIG_CRIS_MACH_ARTPEC3
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#define ETRAXGPIO_IOCTYPE 43
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#define GPIO_MINOR_A 0
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#define GPIO_MINOR_B 1
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#define GPIO_MINOR_LEDS 2
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#define GPIO_MINOR_C 3
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#define GPIO_MINOR_D 4
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#ifdef CONFIG_ETRAX_VIRTUAL_GPIO
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#define GPIO_MINOR_V 6
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#define GPIO_MINOR_LAST 6
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#else
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#define GPIO_MINOR_LAST 4
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#endif
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#define GPIO_MINOR_PWM0 16
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#define GPIO_MINOR_PWM1 17
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#define GPIO_MINOR_PWM2 18
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#define GPIO_MINOR_LAST_PWM GPIO_MINOR_PWM2
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#endif
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/* supported ioctl _IOC_NR's */
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#define IO_READBITS 0x1 /* read and return current port bits (obsolete) */
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#define IO_SETBITS 0x2 /* set the bits marked by 1 in the argument */
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#define IO_CLRBITS 0x3 /* clear the bits marked by 1 in the argument */
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/* the alarm is waited for by select() */
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#define IO_HIGHALARM 0x4 /* set alarm on high for bits marked by 1 */
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#define IO_LOWALARM 0x5 /* set alarm on low for bits marked by 1 */
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#define IO_CLRALARM 0x6 /* clear alarm for bits marked by 1 */
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/* LED ioctl */
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#define IO_LEDACTIVE_SET 0x7 /* set active led
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* 0=off, 1=green, 2=red, 3=yellow */
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/* GPIO direction ioctl's */
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#define IO_READDIR 0x8 /* Read direction 0=input 1=output (obsolete) */
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#define IO_SETINPUT 0x9 /* Set direction for bits set, 0=unchanged 1=input,
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returns mask with current inputs (obsolete) */
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#define IO_SETOUTPUT 0xA /* Set direction for bits set, 0=unchanged 1=output,
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returns mask with current outputs (obsolete)*/
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/* LED ioctl extended */
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#define IO_LED_SETBIT 0xB
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#define IO_LED_CLRBIT 0xC
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/* SHUTDOWN ioctl */
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#define IO_SHUTDOWN 0xD
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#define IO_GET_PWR_BT 0xE
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/* Bit toggling in driver settings */
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/* bit set in low byte0 is CLK mask (0x00FF),
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bit set in byte1 is DATA mask (0xFF00)
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msb, data_mask[7:0] , clk_mask[7:0]
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*/
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#define IO_CFG_WRITE_MODE 0xF
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#define IO_CFG_WRITE_MODE_VALUE(msb, data_mask, clk_mask) \
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( (((msb)&1) << 16) | (((data_mask) &0xFF) << 8) | ((clk_mask) & 0xFF) )
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/* The following 4 ioctl's take a pointer as argument and handles
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* 32 bit ports (port G) properly.
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* These replaces IO_READBITS,IO_SETINPUT AND IO_SETOUTPUT
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*/
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#define IO_READ_INBITS 0x10 /* *arg is result of reading the input pins */
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#define IO_READ_OUTBITS 0x11 /* *arg is result of reading the output shadow */
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#define IO_SETGET_INPUT 0x12 /* bits set in *arg is set to input,
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* *arg updated with current input pins.
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*/
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#define IO_SETGET_OUTPUT 0x13 /* bits set in *arg is set to output,
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* *arg updated with current output pins.
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*/
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/* The following ioctl's are applicable to the PWM channels only */
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#define IO_PWM_SET_MODE 0x20
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enum io_pwm_mode {
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PWM_OFF = 0, /* disabled, deallocated */
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PWM_STANDARD = 1, /* 390 kHz, duty cycle 0..255/256 */
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PWM_FAST = 2, /* variable freq, w/ 10ns active pulse len */
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PWM_VARFREQ = 3 /* individually configurable high/low periods */
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};
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struct io_pwm_set_mode {
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enum io_pwm_mode mode;
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};
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/* Only for mode PWM_VARFREQ. Period lo/high set in increments of 10ns
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* from 10ns (value = 0) to 81920ns (value = 8191)
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* (Resulting frequencies range from 50 MHz (10ns + 10ns) down to
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* 6.1 kHz (81920ns + 81920ns) at 50% duty cycle, to 12.2 kHz at min/max duty
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* cycle (81920 + 10ns or 10ns + 81920ns, respectively).)
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*/
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#define IO_PWM_SET_PERIOD 0x21
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struct io_pwm_set_period {
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int lo; /* 0..8191 */
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int hi; /* 0..8191 */
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};
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/* Only for modes PWM_STANDARD and PWM_FAST.
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* For PWM_STANDARD, set duty cycle of 390 kHz PWM output signal, from
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* 0 (value = 0) to 255/256 (value = 255).
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* For PWM_FAST, set duty cycle of PWM output signal from
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* 0% (value = 0) to 100% (value = 255). Output signal in this mode
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* is a 10ns pulse surrounded by a high or low level depending on duty
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* cycle (except for 0% and 100% which result in a constant output).
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* Resulting output frequency varies from 50 MHz at 50% duty cycle,
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* down to 390 kHz at min/max duty cycle.
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*/
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#define IO_PWM_SET_DUTY 0x22
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struct io_pwm_set_duty {
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int duty; /* 0..255 */
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};
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#endif
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