forked from luck/tmp_suning_uos_patched
2259a819a8
This driver sets the broadcast tick quite early on during probe and does not clean up again in cast of failure. This patch moves the setup call after the registration, placing the on_each_cpu() calls within the global CPU lock region. Signed-off-by: Richard Cochran <rcochran@linutronix.de> Signed-off-by: Len Brown <len.brown@intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
1266 lines
31 KiB
C
1266 lines
31 KiB
C
/*
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* intel_idle.c - native hardware idle loop for modern Intel processors
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*
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* Copyright (c) 2013, Intel Corporation.
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* Len Brown <len.brown@intel.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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/*
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* intel_idle is a cpuidle driver that loads on specific Intel processors
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* in lieu of the legacy ACPI processor_idle driver. The intent is to
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* make Linux more efficient on these processors, as intel_idle knows
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* more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
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*/
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/*
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* Design Assumptions
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*
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* All CPUs have same idle states as boot CPU
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*
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* Chipset BM_STS (bus master status) bit is a NOP
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* for preventing entry into deep C-stats
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*/
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/*
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* Known limitations
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*
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* The driver currently initializes for_each_online_cpu() upon modprobe.
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* It it unaware of subsequent processors hot-added to the system.
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* This means that if you boot with maxcpus=n and later online
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* processors above n, those processors will use C1 only.
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*
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* ACPI has a .suspend hack to turn off deep c-statees during suspend
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* to avoid complications with the lapic timer workaround.
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* Have not seen issues with suspend, but may need same workaround here.
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*
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* There is currently no kernel-based automatic probing/loading mechanism
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* if the driver is built as a module.
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*/
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/* un-comment DEBUG to enable pr_debug() statements */
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#define DEBUG
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#include <linux/kernel.h>
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#include <linux/cpuidle.h>
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#include <linux/tick.h>
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#include <trace/events/power.h>
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#include <linux/sched.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <asm/cpu_device_id.h>
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#include <asm/mwait.h>
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#include <asm/msr.h>
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#define INTEL_IDLE_VERSION "0.4.1"
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#define PREFIX "intel_idle: "
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static struct cpuidle_driver intel_idle_driver = {
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.name = "intel_idle",
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.owner = THIS_MODULE,
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};
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/* intel_idle.max_cstate=0 disables driver */
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static int max_cstate = CPUIDLE_STATE_MAX - 1;
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static unsigned int mwait_substates;
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#define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
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/* Reliable LAPIC Timer States, bit 1 for C1 etc. */
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static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
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struct idle_cpu {
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struct cpuidle_state *state_table;
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/*
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* Hardware C-state auto-demotion may not always be optimal.
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* Indicate which enable bits to clear here.
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*/
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unsigned long auto_demotion_disable_flags;
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bool byt_auto_demotion_disable_flag;
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bool disable_promotion_to_c1e;
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};
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static const struct idle_cpu *icpu;
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static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
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static int intel_idle(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static void intel_idle_freeze(struct cpuidle_device *dev,
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struct cpuidle_driver *drv, int index);
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static int intel_idle_cpu_init(int cpu);
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static struct cpuidle_state *cpuidle_state_table;
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/*
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* Set this flag for states where the HW flushes the TLB for us
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* and so we don't need cross-calls to keep it consistent.
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* If this flag is set, SW flushes the TLB, so even if the
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* HW doesn't do the flushing, this flag is safe to use.
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*/
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#define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
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/*
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* MWAIT takes an 8-bit "hint" in EAX "suggesting"
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* the C-state (top nibble) and sub-state (bottom nibble)
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* 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
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*
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* We store the hint at the top of our "flags" for each state.
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*/
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#define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
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#define MWAIT2flg(eax) ((eax & 0xFF) << 24)
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/*
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* States are indexed by the cstate number,
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* which is also the index into the MWAIT hint array.
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* Thus C0 is a dummy.
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*/
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static struct cpuidle_state nehalem_cstates[] = {
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{
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.name = "C1-NHM",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 3,
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.target_residency = 6,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-NHM",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-NHM",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 20,
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.target_residency = 80,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-NHM",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.target_residency = 800,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state snb_cstates[] = {
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{
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.name = "C1-SNB",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 2,
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.target_residency = 2,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-SNB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-SNB",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 211,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-SNB",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 104,
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.target_residency = 345,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-SNB",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 109,
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.target_residency = 345,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state byt_cstates[] = {
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{
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.name = "C1-BYT",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6N-BYT",
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.desc = "MWAIT 0x58",
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.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 300,
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.target_residency = 275,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6S-BYT",
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.desc = "MWAIT 0x52",
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.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 500,
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.target_residency = 560,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-BYT",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 1200,
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.target_residency = 4000,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7S-BYT",
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.desc = "MWAIT 0x64",
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.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 10000,
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.target_residency = 20000,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state cht_cstates[] = {
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{
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.name = "C1-CHT",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6N-CHT",
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.desc = "MWAIT 0x58",
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.flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 275,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6S-CHT",
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.desc = "MWAIT 0x52",
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.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 200,
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.target_residency = 560,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-CHT",
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.desc = "MWAIT 0x60",
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.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 1200,
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.target_residency = 4000,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7S-CHT",
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.desc = "MWAIT 0x64",
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.flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 10000,
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.target_residency = 20000,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state ivb_cstates[] = {
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{
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.name = "C1-IVB",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVB",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 20,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVB",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 156,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVB",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 80,
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.target_residency = 300,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C7-IVB",
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.desc = "MWAIT 0x30",
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.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 87,
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.target_residency = 300,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state ivt_cstates[] = {
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{
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.name = "C1-IVT",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVT",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 80,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVT",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 156,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVT",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 82,
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.target_residency = 300,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state ivt_cstates_4s[] = {
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{
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.name = "C1-IVT-4S",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C1E-IVT-4S",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 250,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVT-4S",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 300,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C6-IVT-4S",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 84,
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.target_residency = 400,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.enter = NULL }
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};
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static struct cpuidle_state ivt_cstates_8s[] = {
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{
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.name = "C1-IVT-8S",
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.desc = "MWAIT 0x00",
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.flags = MWAIT2flg(0x00),
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.exit_latency = 1,
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.target_residency = 1,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
|
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{
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.name = "C1E-IVT-8S",
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.desc = "MWAIT 0x01",
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.flags = MWAIT2flg(0x01),
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.exit_latency = 10,
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.target_residency = 500,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
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{
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.name = "C3-IVT-8S",
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.desc = "MWAIT 0x10",
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.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 59,
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.target_residency = 600,
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.enter = &intel_idle,
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.enter_freeze = intel_idle_freeze, },
|
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{
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.name = "C6-IVT-8S",
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.desc = "MWAIT 0x20",
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.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
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.exit_latency = 88,
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.target_residency = 700,
|
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.enter = &intel_idle,
|
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.enter_freeze = intel_idle_freeze, },
|
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{
|
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.enter = NULL }
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};
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|
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static struct cpuidle_state hsw_cstates[] = {
|
|
{
|
|
.name = "C1-HSW",
|
|
.desc = "MWAIT 0x00",
|
|
.flags = MWAIT2flg(0x00),
|
|
.exit_latency = 2,
|
|
.target_residency = 2,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C1E-HSW",
|
|
.desc = "MWAIT 0x01",
|
|
.flags = MWAIT2flg(0x01),
|
|
.exit_latency = 10,
|
|
.target_residency = 20,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C3-HSW",
|
|
.desc = "MWAIT 0x10",
|
|
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 33,
|
|
.target_residency = 100,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C6-HSW",
|
|
.desc = "MWAIT 0x20",
|
|
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 133,
|
|
.target_residency = 400,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C7s-HSW",
|
|
.desc = "MWAIT 0x32",
|
|
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 166,
|
|
.target_residency = 500,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C8-HSW",
|
|
.desc = "MWAIT 0x40",
|
|
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 300,
|
|
.target_residency = 900,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C9-HSW",
|
|
.desc = "MWAIT 0x50",
|
|
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 600,
|
|
.target_residency = 1800,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C10-HSW",
|
|
.desc = "MWAIT 0x60",
|
|
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 2600,
|
|
.target_residency = 7700,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.enter = NULL }
|
|
};
|
|
static struct cpuidle_state bdw_cstates[] = {
|
|
{
|
|
.name = "C1-BDW",
|
|
.desc = "MWAIT 0x00",
|
|
.flags = MWAIT2flg(0x00),
|
|
.exit_latency = 2,
|
|
.target_residency = 2,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C1E-BDW",
|
|
.desc = "MWAIT 0x01",
|
|
.flags = MWAIT2flg(0x01),
|
|
.exit_latency = 10,
|
|
.target_residency = 20,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C3-BDW",
|
|
.desc = "MWAIT 0x10",
|
|
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 40,
|
|
.target_residency = 100,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C6-BDW",
|
|
.desc = "MWAIT 0x20",
|
|
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 133,
|
|
.target_residency = 400,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C7s-BDW",
|
|
.desc = "MWAIT 0x32",
|
|
.flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 166,
|
|
.target_residency = 500,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C8-BDW",
|
|
.desc = "MWAIT 0x40",
|
|
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 300,
|
|
.target_residency = 900,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C9-BDW",
|
|
.desc = "MWAIT 0x50",
|
|
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 600,
|
|
.target_residency = 1800,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C10-BDW",
|
|
.desc = "MWAIT 0x60",
|
|
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 2600,
|
|
.target_residency = 7700,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.enter = NULL }
|
|
};
|
|
|
|
static struct cpuidle_state skl_cstates[] = {
|
|
{
|
|
.name = "C1-SKL",
|
|
.desc = "MWAIT 0x00",
|
|
.flags = MWAIT2flg(0x00),
|
|
.exit_latency = 2,
|
|
.target_residency = 2,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C1E-SKL",
|
|
.desc = "MWAIT 0x01",
|
|
.flags = MWAIT2flg(0x01),
|
|
.exit_latency = 10,
|
|
.target_residency = 20,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C3-SKL",
|
|
.desc = "MWAIT 0x10",
|
|
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 70,
|
|
.target_residency = 100,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C6-SKL",
|
|
.desc = "MWAIT 0x20",
|
|
.flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 85,
|
|
.target_residency = 200,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C7s-SKL",
|
|
.desc = "MWAIT 0x33",
|
|
.flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 124,
|
|
.target_residency = 800,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C8-SKL",
|
|
.desc = "MWAIT 0x40",
|
|
.flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 200,
|
|
.target_residency = 800,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C9-SKL",
|
|
.desc = "MWAIT 0x50",
|
|
.flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 480,
|
|
.target_residency = 5000,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C10-SKL",
|
|
.desc = "MWAIT 0x60",
|
|
.flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 890,
|
|
.target_residency = 5000,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.enter = NULL }
|
|
};
|
|
|
|
static struct cpuidle_state atom_cstates[] = {
|
|
{
|
|
.name = "C1E-ATM",
|
|
.desc = "MWAIT 0x00",
|
|
.flags = MWAIT2flg(0x00),
|
|
.exit_latency = 10,
|
|
.target_residency = 20,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C2-ATM",
|
|
.desc = "MWAIT 0x10",
|
|
.flags = MWAIT2flg(0x10),
|
|
.exit_latency = 20,
|
|
.target_residency = 80,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C4-ATM",
|
|
.desc = "MWAIT 0x30",
|
|
.flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 100,
|
|
.target_residency = 400,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C6-ATM",
|
|
.desc = "MWAIT 0x52",
|
|
.flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 140,
|
|
.target_residency = 560,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.enter = NULL }
|
|
};
|
|
static struct cpuidle_state avn_cstates[] = {
|
|
{
|
|
.name = "C1-AVN",
|
|
.desc = "MWAIT 0x00",
|
|
.flags = MWAIT2flg(0x00),
|
|
.exit_latency = 2,
|
|
.target_residency = 2,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.name = "C6-AVN",
|
|
.desc = "MWAIT 0x51",
|
|
.flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 15,
|
|
.target_residency = 45,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze, },
|
|
{
|
|
.enter = NULL }
|
|
};
|
|
static struct cpuidle_state knl_cstates[] = {
|
|
{
|
|
.name = "C1-KNL",
|
|
.desc = "MWAIT 0x00",
|
|
.flags = MWAIT2flg(0x00),
|
|
.exit_latency = 1,
|
|
.target_residency = 2,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze },
|
|
{
|
|
.name = "C6-KNL",
|
|
.desc = "MWAIT 0x10",
|
|
.flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
|
|
.exit_latency = 120,
|
|
.target_residency = 500,
|
|
.enter = &intel_idle,
|
|
.enter_freeze = intel_idle_freeze },
|
|
{
|
|
.enter = NULL }
|
|
};
|
|
|
|
/**
|
|
* intel_idle
|
|
* @dev: cpuidle_device
|
|
* @drv: cpuidle driver
|
|
* @index: index of cpuidle state
|
|
*
|
|
* Must be called under local_irq_disable().
|
|
*/
|
|
static int intel_idle(struct cpuidle_device *dev,
|
|
struct cpuidle_driver *drv, int index)
|
|
{
|
|
unsigned long ecx = 1; /* break on interrupt flag */
|
|
struct cpuidle_state *state = &drv->states[index];
|
|
unsigned long eax = flg2MWAIT(state->flags);
|
|
unsigned int cstate;
|
|
int cpu = smp_processor_id();
|
|
|
|
cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
|
|
|
|
/*
|
|
* leave_mm() to avoid costly and often unnecessary wakeups
|
|
* for flushing the user TLB's associated with the active mm.
|
|
*/
|
|
if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
|
|
leave_mm(cpu);
|
|
|
|
if (!(lapic_timer_reliable_states & (1 << (cstate))))
|
|
tick_broadcast_enter();
|
|
|
|
mwait_idle_with_hints(eax, ecx);
|
|
|
|
if (!(lapic_timer_reliable_states & (1 << (cstate))))
|
|
tick_broadcast_exit();
|
|
|
|
return index;
|
|
}
|
|
|
|
/**
|
|
* intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
|
|
* @dev: cpuidle_device
|
|
* @drv: cpuidle driver
|
|
* @index: state index
|
|
*/
|
|
static void intel_idle_freeze(struct cpuidle_device *dev,
|
|
struct cpuidle_driver *drv, int index)
|
|
{
|
|
unsigned long ecx = 1; /* break on interrupt flag */
|
|
unsigned long eax = flg2MWAIT(drv->states[index].flags);
|
|
|
|
mwait_idle_with_hints(eax, ecx);
|
|
}
|
|
|
|
static void __setup_broadcast_timer(void *arg)
|
|
{
|
|
unsigned long on = (unsigned long)arg;
|
|
|
|
if (on)
|
|
tick_broadcast_enable();
|
|
else
|
|
tick_broadcast_disable();
|
|
}
|
|
|
|
static int cpu_hotplug_notify(struct notifier_block *n,
|
|
unsigned long action, void *hcpu)
|
|
{
|
|
int hotcpu = (unsigned long)hcpu;
|
|
struct cpuidle_device *dev;
|
|
|
|
switch (action & ~CPU_TASKS_FROZEN) {
|
|
case CPU_ONLINE:
|
|
|
|
if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
|
|
smp_call_function_single(hotcpu, __setup_broadcast_timer,
|
|
(void *)true, 1);
|
|
|
|
/*
|
|
* Some systems can hotplug a cpu at runtime after
|
|
* the kernel has booted, we have to initialize the
|
|
* driver in this case
|
|
*/
|
|
dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
|
|
if (!dev->registered)
|
|
intel_idle_cpu_init(hotcpu);
|
|
|
|
break;
|
|
}
|
|
return NOTIFY_OK;
|
|
}
|
|
|
|
static struct notifier_block cpu_hotplug_notifier = {
|
|
.notifier_call = cpu_hotplug_notify,
|
|
};
|
|
|
|
static void auto_demotion_disable(void *dummy)
|
|
{
|
|
unsigned long long msr_bits;
|
|
|
|
rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
|
|
msr_bits &= ~(icpu->auto_demotion_disable_flags);
|
|
wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
|
|
}
|
|
static void c1e_promotion_disable(void *dummy)
|
|
{
|
|
unsigned long long msr_bits;
|
|
|
|
rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
|
|
msr_bits &= ~0x2;
|
|
wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
|
|
}
|
|
|
|
static const struct idle_cpu idle_cpu_nehalem = {
|
|
.state_table = nehalem_cstates,
|
|
.auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_atom = {
|
|
.state_table = atom_cstates,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_lincroft = {
|
|
.state_table = atom_cstates,
|
|
.auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_snb = {
|
|
.state_table = snb_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_byt = {
|
|
.state_table = byt_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
.byt_auto_demotion_disable_flag = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_cht = {
|
|
.state_table = cht_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
.byt_auto_demotion_disable_flag = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_ivb = {
|
|
.state_table = ivb_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_ivt = {
|
|
.state_table = ivt_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_hsw = {
|
|
.state_table = hsw_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_bdw = {
|
|
.state_table = bdw_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_skl = {
|
|
.state_table = skl_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
|
|
static const struct idle_cpu idle_cpu_avn = {
|
|
.state_table = avn_cstates,
|
|
.disable_promotion_to_c1e = true,
|
|
};
|
|
|
|
static const struct idle_cpu idle_cpu_knl = {
|
|
.state_table = knl_cstates,
|
|
};
|
|
|
|
#define ICPU(model, cpu) \
|
|
{ X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
|
|
|
|
static const struct x86_cpu_id intel_idle_ids[] __initconst = {
|
|
ICPU(0x1a, idle_cpu_nehalem),
|
|
ICPU(0x1e, idle_cpu_nehalem),
|
|
ICPU(0x1f, idle_cpu_nehalem),
|
|
ICPU(0x25, idle_cpu_nehalem),
|
|
ICPU(0x2c, idle_cpu_nehalem),
|
|
ICPU(0x2e, idle_cpu_nehalem),
|
|
ICPU(0x1c, idle_cpu_atom),
|
|
ICPU(0x26, idle_cpu_lincroft),
|
|
ICPU(0x2f, idle_cpu_nehalem),
|
|
ICPU(0x2a, idle_cpu_snb),
|
|
ICPU(0x2d, idle_cpu_snb),
|
|
ICPU(0x36, idle_cpu_atom),
|
|
ICPU(0x37, idle_cpu_byt),
|
|
ICPU(0x4c, idle_cpu_cht),
|
|
ICPU(0x3a, idle_cpu_ivb),
|
|
ICPU(0x3e, idle_cpu_ivt),
|
|
ICPU(0x3c, idle_cpu_hsw),
|
|
ICPU(0x3f, idle_cpu_hsw),
|
|
ICPU(0x45, idle_cpu_hsw),
|
|
ICPU(0x46, idle_cpu_hsw),
|
|
ICPU(0x4d, idle_cpu_avn),
|
|
ICPU(0x3d, idle_cpu_bdw),
|
|
ICPU(0x47, idle_cpu_bdw),
|
|
ICPU(0x4f, idle_cpu_bdw),
|
|
ICPU(0x56, idle_cpu_bdw),
|
|
ICPU(0x4e, idle_cpu_skl),
|
|
ICPU(0x5e, idle_cpu_skl),
|
|
ICPU(0x57, idle_cpu_knl),
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
|
|
|
|
/*
|
|
* intel_idle_probe()
|
|
*/
|
|
static int __init intel_idle_probe(void)
|
|
{
|
|
unsigned int eax, ebx, ecx;
|
|
const struct x86_cpu_id *id;
|
|
|
|
if (max_cstate == 0) {
|
|
pr_debug(PREFIX "disabled\n");
|
|
return -EPERM;
|
|
}
|
|
|
|
id = x86_match_cpu(intel_idle_ids);
|
|
if (!id) {
|
|
if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
|
|
boot_cpu_data.x86 == 6)
|
|
pr_debug(PREFIX "does not run on family %d model %d\n",
|
|
boot_cpu_data.x86, boot_cpu_data.x86_model);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
|
|
return -ENODEV;
|
|
|
|
cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
|
|
|
|
if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
|
|
!(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
|
|
!mwait_substates)
|
|
return -ENODEV;
|
|
|
|
pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
|
|
|
|
icpu = (const struct idle_cpu *)id->driver_data;
|
|
cpuidle_state_table = icpu->state_table;
|
|
|
|
pr_debug(PREFIX "v" INTEL_IDLE_VERSION
|
|
" model 0x%X\n", boot_cpu_data.x86_model);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* intel_idle_cpuidle_devices_uninit()
|
|
* Unregisters the cpuidle devices.
|
|
*/
|
|
static void intel_idle_cpuidle_devices_uninit(void)
|
|
{
|
|
int i;
|
|
struct cpuidle_device *dev;
|
|
|
|
for_each_online_cpu(i) {
|
|
dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
|
|
cpuidle_unregister_device(dev);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* ivt_idle_state_table_update(void)
|
|
*
|
|
* Tune IVT multi-socket targets
|
|
* Assumption: num_sockets == (max_package_num + 1)
|
|
*/
|
|
static void ivt_idle_state_table_update(void)
|
|
{
|
|
/* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
|
|
int cpu, package_num, num_sockets = 1;
|
|
|
|
for_each_online_cpu(cpu) {
|
|
package_num = topology_physical_package_id(cpu);
|
|
if (package_num + 1 > num_sockets) {
|
|
num_sockets = package_num + 1;
|
|
|
|
if (num_sockets > 4) {
|
|
cpuidle_state_table = ivt_cstates_8s;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
if (num_sockets > 2)
|
|
cpuidle_state_table = ivt_cstates_4s;
|
|
|
|
/* else, 1 and 2 socket systems use default ivt_cstates */
|
|
}
|
|
/*
|
|
* sklh_idle_state_table_update(void)
|
|
*
|
|
* On SKL-H (model 0x5e) disable C8 and C9 if:
|
|
* C10 is enabled and SGX disabled
|
|
*/
|
|
static void sklh_idle_state_table_update(void)
|
|
{
|
|
unsigned long long msr;
|
|
unsigned int eax, ebx, ecx, edx;
|
|
|
|
|
|
/* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
|
|
if (max_cstate <= 7)
|
|
return;
|
|
|
|
/* if PC10 not present in CPUID.MWAIT.EDX */
|
|
if ((mwait_substates & (0xF << 28)) == 0)
|
|
return;
|
|
|
|
rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr);
|
|
|
|
/* PC10 is not enabled in PKG C-state limit */
|
|
if ((msr & 0xF) != 8)
|
|
return;
|
|
|
|
ecx = 0;
|
|
cpuid(7, &eax, &ebx, &ecx, &edx);
|
|
|
|
/* if SGX is present */
|
|
if (ebx & (1 << 2)) {
|
|
|
|
rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
|
|
|
|
/* if SGX is enabled */
|
|
if (msr & (1 << 18))
|
|
return;
|
|
}
|
|
|
|
skl_cstates[5].disabled = 1; /* C8-SKL */
|
|
skl_cstates[6].disabled = 1; /* C9-SKL */
|
|
}
|
|
/*
|
|
* intel_idle_state_table_update()
|
|
*
|
|
* Update the default state_table for this CPU-id
|
|
*/
|
|
|
|
static void intel_idle_state_table_update(void)
|
|
{
|
|
switch (boot_cpu_data.x86_model) {
|
|
|
|
case 0x3e: /* IVT */
|
|
ivt_idle_state_table_update();
|
|
break;
|
|
case 0x5e: /* SKL-H */
|
|
sklh_idle_state_table_update();
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* intel_idle_cpuidle_driver_init()
|
|
* allocate, initialize cpuidle_states
|
|
*/
|
|
static void __init intel_idle_cpuidle_driver_init(void)
|
|
{
|
|
int cstate;
|
|
struct cpuidle_driver *drv = &intel_idle_driver;
|
|
|
|
intel_idle_state_table_update();
|
|
|
|
drv->state_count = 1;
|
|
|
|
for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
|
|
int num_substates, mwait_hint, mwait_cstate;
|
|
|
|
if ((cpuidle_state_table[cstate].enter == NULL) &&
|
|
(cpuidle_state_table[cstate].enter_freeze == NULL))
|
|
break;
|
|
|
|
if (cstate + 1 > max_cstate) {
|
|
printk(PREFIX "max_cstate %d reached\n",
|
|
max_cstate);
|
|
break;
|
|
}
|
|
|
|
mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
|
|
mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
|
|
|
|
/* number of sub-states for this state in CPUID.MWAIT */
|
|
num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
|
|
& MWAIT_SUBSTATE_MASK;
|
|
|
|
/* if NO sub-states for this state in CPUID, skip it */
|
|
if (num_substates == 0)
|
|
continue;
|
|
|
|
/* if state marked as disabled, skip it */
|
|
if (cpuidle_state_table[cstate].disabled != 0) {
|
|
pr_debug(PREFIX "state %s is disabled",
|
|
cpuidle_state_table[cstate].name);
|
|
continue;
|
|
}
|
|
|
|
|
|
if (((mwait_cstate + 1) > 2) &&
|
|
!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
|
|
mark_tsc_unstable("TSC halts in idle"
|
|
" states deeper than C2");
|
|
|
|
drv->states[drv->state_count] = /* structure copy */
|
|
cpuidle_state_table[cstate];
|
|
|
|
drv->state_count += 1;
|
|
}
|
|
|
|
if (icpu->byt_auto_demotion_disable_flag) {
|
|
wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
|
|
wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* intel_idle_cpu_init()
|
|
* allocate, initialize, register cpuidle_devices
|
|
* @cpu: cpu/core to initialize
|
|
*/
|
|
static int intel_idle_cpu_init(int cpu)
|
|
{
|
|
struct cpuidle_device *dev;
|
|
|
|
dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
|
|
|
|
dev->cpu = cpu;
|
|
|
|
if (cpuidle_register_device(dev)) {
|
|
pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
|
|
intel_idle_cpuidle_devices_uninit();
|
|
return -EIO;
|
|
}
|
|
|
|
if (icpu->auto_demotion_disable_flags)
|
|
smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
|
|
|
|
if (icpu->disable_promotion_to_c1e)
|
|
smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int __init intel_idle_init(void)
|
|
{
|
|
int retval, i;
|
|
|
|
/* Do not load intel_idle at all for now if idle= is passed */
|
|
if (boot_option_idle_override != IDLE_NO_OVERRIDE)
|
|
return -ENODEV;
|
|
|
|
retval = intel_idle_probe();
|
|
if (retval)
|
|
return retval;
|
|
|
|
intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
|
|
if (intel_idle_cpuidle_devices == NULL)
|
|
return -ENOMEM;
|
|
|
|
intel_idle_cpuidle_driver_init();
|
|
retval = cpuidle_register_driver(&intel_idle_driver);
|
|
if (retval) {
|
|
struct cpuidle_driver *drv = cpuidle_get_driver();
|
|
printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
|
|
drv ? drv->name : "none");
|
|
free_percpu(intel_idle_cpuidle_devices);
|
|
return retval;
|
|
}
|
|
|
|
cpu_notifier_register_begin();
|
|
|
|
for_each_online_cpu(i) {
|
|
retval = intel_idle_cpu_init(i);
|
|
if (retval) {
|
|
cpu_notifier_register_done();
|
|
cpuidle_unregister_driver(&intel_idle_driver);
|
|
free_percpu(intel_idle_cpuidle_devices);
|
|
return retval;
|
|
}
|
|
}
|
|
__register_cpu_notifier(&cpu_hotplug_notifier);
|
|
|
|
if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
|
|
lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
|
|
else
|
|
on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
|
|
|
|
cpu_notifier_register_done();
|
|
|
|
pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
|
|
lapic_timer_reliable_states);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit intel_idle_exit(void)
|
|
{
|
|
cpu_notifier_register_begin();
|
|
|
|
if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
|
|
on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
|
|
__unregister_cpu_notifier(&cpu_hotplug_notifier);
|
|
intel_idle_cpuidle_devices_uninit();
|
|
|
|
cpu_notifier_register_done();
|
|
|
|
cpuidle_unregister_driver(&intel_idle_driver);
|
|
free_percpu(intel_idle_cpuidle_devices);
|
|
}
|
|
|
|
module_init(intel_idle_init);
|
|
module_exit(intel_idle_exit);
|
|
|
|
module_param(max_cstate, int, 0444);
|
|
|
|
MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
|
|
MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
|
|
MODULE_LICENSE("GPL");
|