kernel_optimize_test/drivers/clk/renesas
Stephen Boyd 535b1100d1 clk: renesas: Updates for v4.14
- Add more module clocks for R-Car V2H and M3-W,
   - Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
   - Add support for the new R-Car D3 SoC,
   - Allow compile-testing of all (sub)drivers now all dummy infrastructure
     is available,
   - Small fixes and cleanups.
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Merge tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  * Add more module clocks for R-Car V2H and M3-W,
  * Add support for the R-Car Gen3 USB 2.0 clock selector PHY,
  * Add support for the new R-Car D3 SoC,
  * Allow compile-testing of all (sub)drivers now all dummy infrastructure
    is available,
  * Small fixes and cleanups.

* tag 'clk-renesas-for-v4.14-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add USB3.0 clock
  clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY
  clk: renesas: cpg-mssr: Add R8A77995 support
  clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks
  clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3
  clk: renesas: Add r8a77995 CPG Core Clock Definitions
  clk: renesas: rcar-gen3-cpg: Refactor checks for accessing the div table
  clk: renesas: rcar-gen3-cpg: Drop superfluous variable
  clk: renesas: Allow compile-testing of all (sub)drivers
  clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks
  clk: renesas: div6: Document fields used for parent selection
2017-08-23 15:39:58 -07:00
..
clk-div6.c clk: renesas: div6: Document fields used for parent selection 2017-07-17 10:26:48 +02:00
clk-div6.h clk: renesas: div6: use RENESAS for #define 2016-03-15 18:13:02 -07:00
clk-emev2.c
clk-mstp.c clk: Convert to using %pOF instead of full_name 2017-07-21 15:49:54 -07:00
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c clk: renesas: r8a7778: Remove obsolete r8a7778_clocks_init() 2016-11-02 20:44:14 +01:00
clk-r8a7779.c clk: renesas: r8a7779: Remove obsolete r8a7779_clocks_init() 2016-11-02 20:44:17 +01:00
clk-rcar-gen2.c clk: Convert to using %pOF instead of full_name 2017-07-21 15:49:54 -07:00
clk-rz.c clk: renesas: rz: Select EXTAL vs USB clock 2016-09-05 14:16:25 +02:00
clk-sh73a0.c
Kconfig clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY 2017-08-17 09:22:23 +02:00
Makefile clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY 2017-08-17 09:22:23 +02:00
r8a7743-cpg-mssr.c clk: renesas: cpg-mssr: Add R8A7743 support 2016-11-10 15:29:28 +01:00
r8a7745-cpg-mssr.c clk: renesas: r8a7745: Remove PLL configs for MD19=0 2017-05-15 09:46:31 +02:00
r8a7790-cpg-mssr.c clk: renesas: r8a7790: Add new CPG/MSSR driver 2017-05-24 10:19:56 +02:00
r8a7791-cpg-mssr.c clk: renesas: r8a7791/r8a7793: Add new CPG/MSSR driver 2017-05-24 10:19:59 +02:00
r8a7792-cpg-mssr.c clk: renesas: r8a7792: Add IMR-LX3/LSX3 clocks 2017-07-17 10:26:48 +02:00
r8a7794-cpg-mssr.c clk: renesas: r8a7794: Add new CPG/MSSR driver 2017-05-24 10:20:03 +02:00
r8a7795-cpg-mssr.c clk: renesas: rcar-gen3: Add divider support for PLL1 and PLL3 2017-08-16 09:51:47 +02:00
r8a7796-cpg-mssr.c clk: renesas: r8a7796: Add USB3.0 clock 2017-08-17 09:22:26 +02:00
r8a77995-cpg-mssr.c clk: renesas: cpg-mssr: Add R8A77995 support 2017-08-16 09:51:48 +02:00
rcar-gen2-cpg.c clk: renesas: cpg-mssr: Add common R-Car Gen2 support 2016-11-10 15:29:25 +01:00
rcar-gen2-cpg.h clk: renesas: cpg-mssr: Add common R-Car Gen2 support 2016-11-10 15:29:25 +01:00
rcar-gen3-cpg.c clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks 2017-08-16 09:51:47 +02:00
rcar-gen3-cpg.h clk: renesas: rcar-gen3: Add support for SCCG/Clean peripheral clocks 2017-08-16 09:51:47 +02:00
rcar-usb2-clock-sel.c clk: renesas: rcar-usb2-clock-sel: Add R-Car USB 2.0 clock selector PHY 2017-08-17 09:22:23 +02:00
renesas-cpg-mssr.c clk: renesas: cpg-mssr: Add R8A77995 support 2017-08-16 09:51:48 +02:00
renesas-cpg-mssr.h clk: renesas: cpg-mssr: Add R8A77995 support 2017-08-16 09:51:48 +02:00