forked from luck/tmp_suning_uos_patched
265d5e48dd
Patch from Nicolas Pitre
Commit f4619025a5 broke the kernel
decompressor (at least on PXA). Here's the fix.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
722 lines
16 KiB
ArmAsm
722 lines
16 KiB
ArmAsm
/*
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* linux/arch/arm/boot/compressed/head.S
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*
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* Copyright (C) 1996-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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/*
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* Debugging stuff
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*
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* Note that these macros must not contain any code which is not
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* 100% relocatable. Any attempt to do so will result in a crash.
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* Please select one of the following when turning on debugging.
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*/
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#ifdef DEBUG
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#if defined(CONFIG_DEBUG_ICEDCC)
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.macro loadsp, rb
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.endm
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.macro writeb, ch, rb
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mcr p14, 0, \ch, c0, c1, 0
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.endm
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#else
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#include <asm/arch/debug-macro.S>
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.macro writeb, ch, rb
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senduart \ch, \rb
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.endm
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#if defined(CONFIG_ARCH_SA1100)
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.macro loadsp, rb
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mov \rb, #0x80000000 @ physical base address
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#ifdef CONFIG_DEBUG_LL_SER3
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add \rb, \rb, #0x00050000 @ Ser3
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#else
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add \rb, \rb, #0x00010000 @ Ser1
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#endif
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.endm
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#elif defined(CONFIG_ARCH_IOP331)
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.macro loadsp, rb
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mov \rb, #0xff000000
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orr \rb, \rb, #0x00ff0000
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orr \rb, \rb, #0x0000f700 @ location of the UART
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.endm
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#elif defined(CONFIG_ARCH_S3C2410)
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.macro loadsp, rb
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mov \rb, #0x50000000
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add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
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.endm
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#else
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.macro loadsp, rb
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addruart \rb
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.endm
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#endif
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#endif
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#endif
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.macro kputc,val
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mov r0, \val
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bl putc
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.endm
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.macro kphex,val,len
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mov r0, \val
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mov r1, #\len
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bl phex
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.endm
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.macro debug_reloc_start
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#ifdef DEBUG
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kputc #'\n'
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kphex r6, 8 /* processor id */
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kputc #':'
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kphex r7, 8 /* architecture id */
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kputc #':'
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mrc p15, 0, r0, c1, c0
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kphex r0, 8 /* control reg */
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kputc #'\n'
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kphex r5, 8 /* decompressed kernel start */
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kputc #'-'
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kphex r9, 8 /* decompressed kernel end */
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kputc #'>'
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kphex r4, 8 /* kernel execution address */
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kputc #'\n'
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#endif
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.endm
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.macro debug_reloc_end
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#ifdef DEBUG
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kphex r5, 8 /* end of kernel */
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kputc #'\n'
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mov r0, r4
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bl memdump /* dump 256 bytes at start of kernel */
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#endif
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.endm
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.section ".start", #alloc, #execinstr
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/*
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* sort out different calling conventions
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*/
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.align
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start:
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.type start,#function
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.rept 8
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mov r0, r0
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.endr
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b 1f
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.word 0x016f2818 @ Magic numbers to help the loader
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.word start @ absolute load/run zImage address
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.word _edata @ zImage end address
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1: mov r7, r1 @ save architecture ID
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mov r8, r2 @ save atags pointer
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#ifndef __ARM_ARCH_2__
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/*
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* Booting from Angel - need to enter SVC mode and disable
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* FIQs/IRQs (numeric definitions from angel arm.h source).
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* We only do this if we were in user mode on entry.
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*/
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mrs r2, cpsr @ get current mode
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tst r2, #3 @ not user?
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bne not_angel
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mov r0, #0x17 @ angel_SWIreason_EnterSVC
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swi 0x123456 @ angel_SWI_ARM
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not_angel:
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mrs r2, cpsr @ turn off interrupts to
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orr r2, r2, #0xc0 @ prevent angel from running
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msr cpsr_c, r2
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#else
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teqp pc, #0x0c000003 @ turn off interrupts
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#endif
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/*
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* Note that some cache flushing and other stuff may
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* be needed here - is there an Angel SWI call for this?
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*/
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/*
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* some architecture specific code can be inserted
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* by the linker here, but it should preserve r7, r8, and r9.
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*/
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.text
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adr r0, LC0
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ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
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subs r0, r0, r1 @ calculate the delta offset
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@ if delta is zero, we are
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beq not_relocated @ running at the address we
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@ were linked at.
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/*
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* We're running at a different address. We need to fix
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* up various pointers:
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* r5 - zImage base address
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* r6 - GOT start
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* ip - GOT end
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*/
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add r5, r5, r0
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add r6, r6, r0
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add ip, ip, r0
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#ifndef CONFIG_ZBOOT_ROM
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/*
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* If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
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* we need to fix up pointers into the BSS region.
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* r2 - BSS start
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* r3 - BSS end
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* sp - stack pointer
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*/
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add r2, r2, r0
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add r3, r3, r0
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add sp, sp, r0
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/*
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* Relocate all entries in the GOT table.
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*/
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1: ldr r1, [r6, #0] @ relocate entries in the GOT
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add r1, r1, r0 @ table. This fixes up the
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str r1, [r6], #4 @ C references.
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cmp r6, ip
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blo 1b
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#else
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/*
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* Relocate entries in the GOT table. We only relocate
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* the entries that are outside the (relocated) BSS region.
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*/
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1: ldr r1, [r6, #0] @ relocate entries in the GOT
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cmp r1, r2 @ entry < bss_start ||
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cmphs r3, r1 @ _end < entry
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addlo r1, r1, r0 @ table. This fixes up the
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str r1, [r6], #4 @ C references.
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cmp r6, ip
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blo 1b
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#endif
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not_relocated: mov r0, #0
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1: str r0, [r2], #4 @ clear bss
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str r0, [r2], #4
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str r0, [r2], #4
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str r0, [r2], #4
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cmp r2, r3
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blo 1b
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/*
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* The C runtime environment should now be setup
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* sufficiently. Turn the cache on, set up some
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* pointers, and start decompressing.
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*/
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bl cache_on
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mov r1, sp @ malloc space above stack
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add r2, sp, #0x10000 @ 64k max
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/*
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* Check to see if we will overwrite ourselves.
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* r4 = final kernel address
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* r5 = start of this image
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* r2 = end of malloc space (and therefore this image)
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* We basically want:
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* r4 >= r2 -> OK
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* r4 + image length <= r5 -> OK
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*/
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cmp r4, r2
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bhs wont_overwrite
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add r0, r4, #4096*1024 @ 4MB largest kernel size
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cmp r0, r5
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bls wont_overwrite
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mov r5, r2 @ decompress after malloc space
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mov r0, r5
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mov r3, r7
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bl decompress_kernel
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add r0, r0, #127
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bic r0, r0, #127 @ align the kernel length
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/*
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* r0 = decompressed kernel length
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* r1-r3 = unused
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* r4 = kernel execution address
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* r5 = decompressed kernel start
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* r6 = processor ID
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* r7 = architecture ID
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* r8 = atags pointer
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* r9-r14 = corrupted
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*/
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add r1, r5, r0 @ end of decompressed kernel
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adr r2, reloc_start
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ldr r3, LC1
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add r3, r2, r3
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1: ldmia r2!, {r9 - r14} @ copy relocation code
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stmia r1!, {r9 - r14}
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ldmia r2!, {r9 - r14}
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stmia r1!, {r9 - r14}
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cmp r2, r3
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blo 1b
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bl cache_clean_flush
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add pc, r5, r0 @ call relocation code
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/*
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* We're not in danger of overwriting ourselves. Do this the simple way.
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*
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* r4 = kernel execution address
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* r7 = architecture ID
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*/
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wont_overwrite: mov r0, r4
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mov r3, r7
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bl decompress_kernel
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b call_kernel
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.type LC0, #object
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LC0: .word LC0 @ r1
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.word __bss_start @ r2
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.word _end @ r3
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.word zreladdr @ r4
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.word _start @ r5
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.word _got_start @ r6
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.word _got_end @ ip
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.word user_stack+4096 @ sp
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LC1: .word reloc_end - reloc_start
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.size LC0, . - LC0
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#ifdef CONFIG_ARCH_RPC
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.globl params
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params: ldr r0, =params_phys
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mov pc, lr
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.ltorg
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.align
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#endif
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/*
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* Turn on the cache. We need to setup some page tables so that we
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* can have both the I and D caches on.
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*
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* We place the page tables 16k down from the kernel execution address,
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* and we hope that nothing else is using it. If we're using it, we
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* will go pop!
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*
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* On entry,
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* r4 = kernel execution address
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* r6 = processor ID
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* r7 = architecture number
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* r8 = atags pointer
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* r9 = run-time address of "start" (???)
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* On exit,
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* r1, r2, r3, r9, r10, r12 corrupted
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* This routine must preserve:
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* r4, r5, r6, r7, r8
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*/
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.align 5
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cache_on: mov r3, #8 @ cache_on function
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b call_cache_fn
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__setup_mmu: sub r3, r4, #16384 @ Page directory size
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bic r3, r3, #0xff @ Align the pointer
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bic r3, r3, #0x3f00
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/*
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* Initialise the page tables, turning on the cacheable and bufferable
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* bits for the RAM area only.
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*/
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mov r0, r3
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mov r9, r0, lsr #18
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mov r9, r9, lsl #18 @ start of RAM
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add r10, r9, #0x10000000 @ a reasonable RAM size
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mov r1, #0x12
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orr r1, r1, #3 << 10
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add r2, r3, #16384
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1: cmp r1, r9 @ if virt > start of RAM
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orrhs r1, r1, #0x0c @ set cacheable, bufferable
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cmp r1, r10 @ if virt > end of RAM
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bichs r1, r1, #0x0c @ clear cacheable, bufferable
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str r1, [r0], #4 @ 1:1 mapping
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add r1, r1, #1048576
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teq r0, r2
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bne 1b
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/*
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* If ever we are running from Flash, then we surely want the cache
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* to be enabled also for our execution instance... We map 2MB of it
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* so there is no map overlap problem for up to 1 MB compressed kernel.
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* If the execution is in RAM then we would only be duplicating the above.
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*/
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mov r1, #0x1e
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orr r1, r1, #3 << 10
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mov r2, pc, lsr #20
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orr r1, r1, r2, lsl #20
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add r0, r3, r2, lsl #2
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str r1, [r0], #4
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add r1, r1, #1048576
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str r1, [r0]
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mov pc, lr
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__armv4_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
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orr r0, r0, #0x0030
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bl __common_cache_on
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mov r0, #0
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mov pc, r12
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__arm6_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov r0, #0x30
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bl __common_cache_on
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mov r0, #0
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov pc, r12
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__common_cache_on:
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#ifndef DEBUG
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orr r0, r0, #0x000d @ Write buffer, mmu
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#endif
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mov r1, #-1
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mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c3, c0, 0 @ load domain access control
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mcr p15, 0, r0, c1, c0, 0 @ load control register
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mov pc, lr
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/*
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* All code following this line is relocatable. It is relocated by
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* the above code to the end of the decompressed kernel image and
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* executed there. During this time, we have no stacks.
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*
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* r0 = decompressed kernel length
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* r1-r3 = unused
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* r4 = kernel execution address
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* r5 = decompressed kernel start
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* r6 = processor ID
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* r7 = architecture ID
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* r8 = atags pointer
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* r9-r14 = corrupted
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*/
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.align 5
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reloc_start: add r9, r5, r0
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debug_reloc_start
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mov r1, r4
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1:
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.rept 4
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ldmia r5!, {r0, r2, r3, r10 - r14} @ relocate kernel
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stmia r1!, {r0, r2, r3, r10 - r14}
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.endr
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cmp r5, r9
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blo 1b
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debug_reloc_end
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call_kernel: bl cache_clean_flush
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bl cache_off
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mov r0, #0 @ must be zero
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mov r1, r7 @ restore architecture number
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mov r2, r8 @ restore atags pointer
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mov pc, r4 @ call kernel
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/*
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* Here follow the relocatable cache support functions for the
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* various processors. This is a generic hook for locating an
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* entry and jumping to an instruction at the specified offset
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* from the start of the block. Please note this is all position
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* independent code.
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*
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* r1 = corrupted
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* r2 = corrupted
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* r3 = block offset
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* r6 = corrupted
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* r12 = corrupted
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*/
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call_cache_fn: adr r12, proc_types
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mrc p15, 0, r6, c0, c0 @ get processor ID
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1: ldr r1, [r12, #0] @ get value
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ldr r2, [r12, #4] @ get mask
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eor r1, r1, r6 @ (real ^ match)
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tst r1, r2 @ & mask
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addeq pc, r12, r3 @ call cache function
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add r12, r12, #4*5
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b 1b
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/*
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* Table for cache operations. This is basically:
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* - CPU ID match
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* - CPU ID mask
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* - 'cache on' method instruction
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* - 'cache off' method instruction
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* - 'cache flush' method instruction
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*
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* We match an entry using: ((real_id ^ match) & mask) == 0
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*
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* Writethrough caches generally only need 'on' and 'off'
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* methods. Writeback caches _must_ have the flush method
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* defined.
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*/
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.type proc_types,#object
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proc_types:
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.word 0x41560600 @ ARM6/610
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.word 0xffffffe0
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b __arm6_cache_off @ works, but slow
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b __arm6_cache_off
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mov pc, lr
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@ b __arm6_cache_on @ untested
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@ b __arm6_cache_off
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@ b __armv3_cache_flush
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.word 0x00000000 @ old ARM ID
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.word 0x0000f000
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mov pc, lr
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mov pc, lr
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mov pc, lr
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.word 0x41007000 @ ARM7/710
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.word 0xfff8fe00
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b __arm7_cache_off
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b __arm7_cache_off
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mov pc, lr
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.word 0x41807200 @ ARM720T (writethrough)
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.word 0xffffff00
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b __armv4_cache_on
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b __armv4_cache_off
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mov pc, lr
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.word 0x00007000 @ ARM7 IDs
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.word 0x0000f000
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mov pc, lr
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mov pc, lr
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mov pc, lr
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@ Everything from here on will be the new ID system.
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.word 0x4401a100 @ sa110 / sa1100
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.word 0xffffffe0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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.word 0x6901b110 @ sa1110
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.word 0xfffffff0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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@ These match on the architecture ID
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.word 0x00020000 @ ARMv4T
|
|
.word 0x000f0000
|
|
b __armv4_cache_on
|
|
b __armv4_cache_off
|
|
b __armv4_cache_flush
|
|
|
|
.word 0x00050000 @ ARMv5TE
|
|
.word 0x000f0000
|
|
b __armv4_cache_on
|
|
b __armv4_cache_off
|
|
b __armv4_cache_flush
|
|
|
|
.word 0x00060000 @ ARMv5TEJ
|
|
.word 0x000f0000
|
|
b __armv4_cache_on
|
|
b __armv4_cache_off
|
|
b __armv4_cache_flush
|
|
|
|
.word 0x00070000 @ ARMv6
|
|
.word 0x000f0000
|
|
b __armv4_cache_on
|
|
b __armv4_cache_off
|
|
b __armv6_cache_flush
|
|
|
|
.word 0 @ unrecognised type
|
|
.word 0
|
|
mov pc, lr
|
|
mov pc, lr
|
|
mov pc, lr
|
|
|
|
.size proc_types, . - proc_types
|
|
|
|
/*
|
|
* Turn off the Cache and MMU. ARMv3 does not support
|
|
* reading the control register, but ARMv4 does.
|
|
*
|
|
* On entry, r6 = processor ID
|
|
* On exit, r0, r1, r2, r3, r12 corrupted
|
|
* This routine must preserve: r4, r6, r7
|
|
*/
|
|
.align 5
|
|
cache_off: mov r3, #12 @ cache_off function
|
|
b call_cache_fn
|
|
|
|
__armv4_cache_off:
|
|
mrc p15, 0, r0, c1, c0
|
|
bic r0, r0, #0x000d
|
|
mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
|
|
mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
|
|
mov pc, lr
|
|
|
|
__arm6_cache_off:
|
|
mov r0, #0x00000030 @ ARM6 control reg.
|
|
b __armv3_cache_off
|
|
|
|
__arm7_cache_off:
|
|
mov r0, #0x00000070 @ ARM7 control reg.
|
|
b __armv3_cache_off
|
|
|
|
__armv3_cache_off:
|
|
mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
|
|
mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
|
|
mov pc, lr
|
|
|
|
/*
|
|
* Clean and flush the cache to maintain consistency.
|
|
*
|
|
* On entry,
|
|
* r6 = processor ID
|
|
* On exit,
|
|
* r1, r2, r3, r11, r12 corrupted
|
|
* This routine must preserve:
|
|
* r0, r4, r5, r6, r7
|
|
*/
|
|
.align 5
|
|
cache_clean_flush:
|
|
mov r3, #16
|
|
b call_cache_fn
|
|
|
|
__armv6_cache_flush:
|
|
mov r1, #0
|
|
mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
|
|
mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
|
|
mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
|
|
mcr p15, 0, r1, c7, c10, 4 @ drain WB
|
|
mov pc, lr
|
|
|
|
__armv4_cache_flush:
|
|
mov r2, #64*1024 @ default: 32K dcache size (*2)
|
|
mov r11, #32 @ default: 32 byte line size
|
|
mrc p15, 0, r3, c0, c0, 1 @ read cache type
|
|
teq r3, r6 @ cache ID register present?
|
|
beq no_cache_id
|
|
mov r1, r3, lsr #18
|
|
and r1, r1, #7
|
|
mov r2, #1024
|
|
mov r2, r2, lsl r1 @ base dcache size *2
|
|
tst r3, #1 << 14 @ test M bit
|
|
addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
|
|
mov r3, r3, lsr #12
|
|
and r3, r3, #3
|
|
mov r11, #8
|
|
mov r11, r11, lsl r3 @ cache line size in bytes
|
|
no_cache_id:
|
|
bic r1, pc, #63 @ align to longest cache line
|
|
add r2, r1, r2
|
|
1: ldr r3, [r1], r11 @ s/w flush D cache
|
|
teq r1, r2
|
|
bne 1b
|
|
|
|
mcr p15, 0, r1, c7, c5, 0 @ flush I cache
|
|
mcr p15, 0, r1, c7, c6, 0 @ flush D cache
|
|
mcr p15, 0, r1, c7, c10, 4 @ drain WB
|
|
mov pc, lr
|
|
|
|
__armv3_cache_flush:
|
|
mov r1, #0
|
|
mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
|
|
mov pc, lr
|
|
|
|
/*
|
|
* Various debugging routines for printing hex characters and
|
|
* memory, which again must be relocatable.
|
|
*/
|
|
#ifdef DEBUG
|
|
.type phexbuf,#object
|
|
phexbuf: .space 12
|
|
.size phexbuf, . - phexbuf
|
|
|
|
phex: adr r3, phexbuf
|
|
mov r2, #0
|
|
strb r2, [r3, r1]
|
|
1: subs r1, r1, #1
|
|
movmi r0, r3
|
|
bmi puts
|
|
and r2, r0, #15
|
|
mov r0, r0, lsr #4
|
|
cmp r2, #10
|
|
addge r2, r2, #7
|
|
add r2, r2, #'0'
|
|
strb r2, [r3, r1]
|
|
b 1b
|
|
|
|
puts: loadsp r3
|
|
1: ldrb r2, [r0], #1
|
|
teq r2, #0
|
|
moveq pc, lr
|
|
2: writeb r2, r3
|
|
mov r1, #0x00020000
|
|
3: subs r1, r1, #1
|
|
bne 3b
|
|
teq r2, #'\n'
|
|
moveq r2, #'\r'
|
|
beq 2b
|
|
teq r0, #0
|
|
bne 1b
|
|
mov pc, lr
|
|
putc:
|
|
mov r2, r0
|
|
mov r0, #0
|
|
loadsp r3
|
|
b 2b
|
|
|
|
memdump: mov r12, r0
|
|
mov r10, lr
|
|
mov r11, #0
|
|
2: mov r0, r11, lsl #2
|
|
add r0, r0, r12
|
|
mov r1, #8
|
|
bl phex
|
|
mov r0, #':'
|
|
bl putc
|
|
1: mov r0, #' '
|
|
bl putc
|
|
ldr r0, [r12, r11, lsl #2]
|
|
mov r1, #8
|
|
bl phex
|
|
and r0, r11, #7
|
|
teq r0, #3
|
|
moveq r0, #' '
|
|
bleq putc
|
|
and r0, r11, #7
|
|
add r11, r11, #1
|
|
teq r0, #7
|
|
bne 1b
|
|
mov r0, #'\n'
|
|
bl putc
|
|
cmp r11, #64
|
|
blt 2b
|
|
mov pc, r10
|
|
#endif
|
|
|
|
reloc_end:
|
|
|
|
.align
|
|
.section ".stack", "w"
|
|
user_stack: .space 4096
|