forked from luck/tmp_suning_uos_patched
980f2296b5
This updates the IOP platform to use the kernel's generic time framework. With clockevent support in place, this reduces to selecting GENERIC_TIME and removing the platform's private timer ->offset() operation (iop_gettimeoffset). Tested on n2100, compile-tested for all plat-iop machines. Signed-off-by: Mikael Pettersson <mikpe@it.uu.se> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
341 lines
7.6 KiB
C
341 lines
7.6 KiB
C
/*
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* arch/arm/mach-iop32x/iq31244.c
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*
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* Board support code for the Intel EP80219 and IQ31244 platforms.
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*
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* Author: Rory Bolt <rorybolt@pacbell.net>
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* Copyright (C) 2002 Rory Bolt
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* Copyright 2003 (c) MontaVista, Software, Inc.
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* Copyright (C) 2004 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/pm.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/serial_core.h>
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#include <linux/serial_8250.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/time.h>
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#include <asm/mach-types.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <mach/time.h>
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/*
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* Until March of 2007 iq31244 platforms and ep80219 platforms shared the
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* same machine id, and the processor type was used to select board type.
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* However this assumption breaks for an iq80219 board which is an iop219
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* processor on an iq31244 board. The force_ep80219 flag has been added
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* for old boot loaders using the iq31244 machine id for an ep80219 platform.
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*/
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static int force_ep80219;
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static int is_80219(void)
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{
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return !!((read_cpuid_id() & 0xffffffe0) == 0x69052e20);
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}
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static int is_ep80219(void)
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{
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if (machine_is_ep80219() || force_ep80219)
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return 1;
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else
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return 0;
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}
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/*
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* EP80219/IQ31244 timer tick configuration.
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*/
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static void __init iq31244_timer_init(void)
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{
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if (is_ep80219()) {
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/* 33.333 MHz crystal. */
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iop_init_time(200000000);
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} else {
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/* 33.000 MHz crystal. */
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iop_init_time(198000000);
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}
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}
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static struct sys_timer iq31244_timer = {
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.init = iq31244_timer_init,
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};
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/*
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* IQ31244 I/O.
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*/
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static struct map_desc iq31244_io_desc[] __initdata = {
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{ /* on-board devices */
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.virtual = IQ31244_UART,
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.pfn = __phys_to_pfn(IQ31244_UART),
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.length = 0x00100000,
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.type = MT_DEVICE,
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},
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};
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void __init iq31244_map_io(void)
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{
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iop3xx_map_io();
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iotable_init(iq31244_io_desc, ARRAY_SIZE(iq31244_io_desc));
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}
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/*
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* EP80219/IQ31244 PCI.
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*/
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static int __init
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ep80219_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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if (slot == 0) {
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/* CFlash */
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irq = IRQ_IOP32X_XINT1;
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} else if (slot == 1) {
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/* 82551 Pro 100 */
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irq = IRQ_IOP32X_XINT0;
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} else if (slot == 2) {
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/* PCI-X Slot */
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irq = IRQ_IOP32X_XINT3;
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} else if (slot == 3) {
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/* SATA */
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irq = IRQ_IOP32X_XINT2;
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} else {
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printk(KERN_ERR "ep80219_pci_map_irq() called for unknown "
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"device PCI:%d:%d:%d\n", dev->bus->number,
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PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
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irq = -1;
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}
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return irq;
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}
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static struct hw_pci ep80219_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.nr_controllers = 1,
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.setup = iop3xx_pci_setup,
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.preinit = iop3xx_pci_preinit,
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.scan = iop3xx_pci_scan_bus,
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.map_irq = ep80219_pci_map_irq,
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};
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static int __init
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iq31244_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq;
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if (slot == 0) {
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/* CFlash */
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irq = IRQ_IOP32X_XINT1;
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} else if (slot == 1) {
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/* SATA */
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irq = IRQ_IOP32X_XINT2;
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} else if (slot == 2) {
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/* PCI-X Slot */
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irq = IRQ_IOP32X_XINT3;
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} else if (slot == 3) {
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/* 82546 GigE */
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irq = IRQ_IOP32X_XINT0;
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} else {
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printk(KERN_ERR "iq31244_pci_map_irq called for unknown "
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"device PCI:%d:%d:%d\n", dev->bus->number,
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PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
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irq = -1;
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}
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return irq;
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}
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static struct hw_pci iq31244_pci __initdata = {
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.swizzle = pci_std_swizzle,
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.nr_controllers = 1,
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.setup = iop3xx_pci_setup,
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.preinit = iop3xx_pci_preinit,
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.scan = iop3xx_pci_scan_bus,
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.map_irq = iq31244_pci_map_irq,
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};
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static int __init iq31244_pci_init(void)
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{
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if (is_ep80219())
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pci_common_init(&ep80219_pci);
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else if (machine_is_iq31244()) {
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if (is_80219()) {
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printk("note: iq31244 board type has been selected\n");
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printk("note: to select ep80219 operation:\n");
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printk("\t1/ specify \"force_ep80219\" on the kernel"
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" command line\n");
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printk("\t2/ update boot loader to pass"
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" the ep80219 id: %d\n", MACH_TYPE_EP80219);
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}
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pci_common_init(&iq31244_pci);
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}
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return 0;
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}
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subsys_initcall(iq31244_pci_init);
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/*
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* IQ31244 machine initialisation.
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*/
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static struct physmap_flash_data iq31244_flash_data = {
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.width = 2,
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};
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static struct resource iq31244_flash_resource = {
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.start = 0xf0000000,
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.end = 0xf07fffff,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device iq31244_flash_device = {
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.name = "physmap-flash",
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.id = 0,
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.dev = {
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.platform_data = &iq31244_flash_data,
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},
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.num_resources = 1,
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.resource = &iq31244_flash_resource,
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};
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static struct plat_serial8250_port iq31244_serial_port[] = {
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{
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.mapbase = IQ31244_UART,
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.membase = (char *)IQ31244_UART,
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.irq = IRQ_IOP32X_XINT1,
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.flags = UPF_SKIP_TEST,
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.iotype = UPIO_MEM,
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.regshift = 0,
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.uartclk = 1843200,
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},
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{ },
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};
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static struct resource iq31244_uart_resource = {
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.start = IQ31244_UART,
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.end = IQ31244_UART + 7,
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.flags = IORESOURCE_MEM,
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};
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static struct platform_device iq31244_serial_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = iq31244_serial_port,
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},
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.num_resources = 1,
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.resource = &iq31244_uart_resource,
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};
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/*
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* This function will send a SHUTDOWN_COMPLETE message to the PIC
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* controller over I2C. We are not using the i2c subsystem since
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* we are going to power off and it may be removed
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*/
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void ep80219_power_off(void)
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{
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/*
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* Send the Address byte w/ the start condition
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*/
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*IOP3XX_IDBR1 = 0x60;
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*IOP3XX_ICR1 = 0xE9;
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mdelay(1);
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/*
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* Send the START_MSG byte w/ no start or stop condition
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*/
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*IOP3XX_IDBR1 = 0x0F;
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*IOP3XX_ICR1 = 0xE8;
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mdelay(1);
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/*
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* Send the SHUTDOWN_COMPLETE Message ID byte w/ no start or
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* stop condition
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*/
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*IOP3XX_IDBR1 = 0x03;
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*IOP3XX_ICR1 = 0xE8;
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mdelay(1);
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/*
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* Send an ignored byte w/ stop condition
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*/
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*IOP3XX_IDBR1 = 0x00;
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*IOP3XX_ICR1 = 0xEA;
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while (1)
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;
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}
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static void __init iq31244_init_machine(void)
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{
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platform_device_register(&iop3xx_i2c0_device);
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platform_device_register(&iop3xx_i2c1_device);
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platform_device_register(&iq31244_flash_device);
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platform_device_register(&iq31244_serial_device);
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platform_device_register(&iop3xx_dma_0_channel);
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platform_device_register(&iop3xx_dma_1_channel);
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if (is_ep80219())
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pm_power_off = ep80219_power_off;
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if (!is_80219())
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platform_device_register(&iop3xx_aau_channel);
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}
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static int __init force_ep80219_setup(char *str)
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{
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force_ep80219 = 1;
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return 1;
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}
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__setup("force_ep80219", force_ep80219_setup);
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MACHINE_START(IQ31244, "Intel IQ31244")
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/* Maintainer: Intel Corp. */
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.phys_io = IQ31244_UART,
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.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
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.boot_params = 0xa0000100,
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.map_io = iq31244_map_io,
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.init_irq = iop32x_init_irq,
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.timer = &iq31244_timer,
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.init_machine = iq31244_init_machine,
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MACHINE_END
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/* There should have been an ep80219 machine identifier from the beginning.
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* Boot roms older than March 2007 do not know the ep80219 machine id. Pass
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* "force_ep80219" on the kernel command line, otherwise iq31244 operation
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* will be selected.
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*/
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MACHINE_START(EP80219, "Intel EP80219")
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/* Maintainer: Intel Corp. */
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.phys_io = IQ31244_UART,
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.io_pg_offst = ((IQ31244_UART) >> 18) & 0xfffc,
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.boot_params = 0xa0000100,
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.map_io = iq31244_map_io,
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.init_irq = iop32x_init_irq,
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.timer = &iq31244_timer,
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.init_machine = iq31244_init_machine,
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MACHINE_END
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