forked from luck/tmp_suning_uos_patched
288752a8aa
Newer BCM63XX SoCs use virtually the same CPU ID, differing only in the revision bits. But since they all have the Chip ID register at the same location, we can use that to identify the SoC we are running on. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Cc: linux-mips@linux-mips.org Cc: Maxime Bizon <mbizon@freebox.fr> Cc: Florian Fainelli <florian@openwrt.org> Cc: Kevin Cernekee <cernekee@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/3955/ Reviewed-by: Florian Fainelli <florian@openwrt.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
279 lines
6.5 KiB
C
279 lines
6.5 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
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* Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/cpu.h>
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#include <asm/cpu.h>
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#include <asm/cpu-info.h>
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#include <asm/mipsregs.h>
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#include <bcm63xx_cpu.h>
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#include <bcm63xx_regs.h>
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#include <bcm63xx_io.h>
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#include <bcm63xx_irq.h>
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const unsigned long *bcm63xx_regs_base;
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EXPORT_SYMBOL(bcm63xx_regs_base);
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const int *bcm63xx_irqs;
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EXPORT_SYMBOL(bcm63xx_irqs);
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static u16 bcm63xx_cpu_id;
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static u16 bcm63xx_cpu_rev;
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static unsigned int bcm63xx_cpu_freq;
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static unsigned int bcm63xx_memory_size;
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static const unsigned long bcm6338_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6338)
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};
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static const int bcm6338_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6338)
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};
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static const unsigned long bcm6345_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6345)
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};
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static const int bcm6345_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6345)
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};
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static const unsigned long bcm6348_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6348)
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};
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static const int bcm6348_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6348)
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};
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static const unsigned long bcm6358_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6358)
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};
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static const int bcm6358_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6358)
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};
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static const unsigned long bcm6368_regs_base[] = {
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__GEN_CPU_REGS_TABLE(6368)
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};
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static const int bcm6368_irqs[] = {
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__GEN_CPU_IRQ_TABLE(6368)
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};
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u16 __bcm63xx_get_cpu_id(void)
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{
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return bcm63xx_cpu_id;
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}
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EXPORT_SYMBOL(__bcm63xx_get_cpu_id);
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u16 bcm63xx_get_cpu_rev(void)
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{
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return bcm63xx_cpu_rev;
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}
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EXPORT_SYMBOL(bcm63xx_get_cpu_rev);
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unsigned int bcm63xx_get_cpu_freq(void)
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{
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return bcm63xx_cpu_freq;
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}
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unsigned int bcm63xx_get_memory_size(void)
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{
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return bcm63xx_memory_size;
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}
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static unsigned int detect_cpu_clock(void)
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{
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switch (bcm63xx_get_cpu_id()) {
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case BCM6338_CPU_ID:
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/* BCM6338 has a fixed 240 Mhz frequency */
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return 240000000;
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case BCM6345_CPU_ID:
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/* BCM6345 has a fixed 140Mhz frequency */
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return 140000000;
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case BCM6348_CPU_ID:
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{
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unsigned int tmp, n1, n2, m1;
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/* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */
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tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG);
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n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT;
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n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT;
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m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT;
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n1 += 1;
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n2 += 2;
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m1 += 1;
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return (16 * 1000000 * n1 * n2) / m1;
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}
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case BCM6358_CPU_ID:
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{
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unsigned int tmp, n1, n2, m1;
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/* 16MHz * N1 * N2 / M1_CPU */
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tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG);
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n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT;
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n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT;
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m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT;
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return (16 * 1000000 * n1 * n2) / m1;
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}
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case BCM6368_CPU_ID:
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{
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unsigned int tmp, p1, p2, ndiv, m1;
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/* (64MHz / P1) * P2 * NDIV / M1_CPU */
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tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_6368_REG);
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p1 = (tmp & DMIPSPLLCFG_6368_P1_MASK) >>
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DMIPSPLLCFG_6368_P1_SHIFT;
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p2 = (tmp & DMIPSPLLCFG_6368_P2_MASK) >>
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DMIPSPLLCFG_6368_P2_SHIFT;
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ndiv = (tmp & DMIPSPLLCFG_6368_NDIV_MASK) >>
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DMIPSPLLCFG_6368_NDIV_SHIFT;
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tmp = bcm_ddr_readl(DDR_DMIPSPLLDIV_6368_REG);
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m1 = (tmp & DMIPSPLLDIV_6368_MDIV_MASK) >>
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DMIPSPLLDIV_6368_MDIV_SHIFT;
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return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
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}
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default:
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BUG();
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}
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}
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/*
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* attempt to detect the amount of memory installed
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*/
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static unsigned int detect_memory_size(void)
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{
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unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
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u32 val;
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if (BCMCPU_IS_6345()) {
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val = bcm_sdram_readl(SDRAM_MBASE_REG);
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return (val * 8 * 1024 * 1024);
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}
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if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
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val = bcm_sdram_readl(SDRAM_CFG_REG);
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rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
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cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
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is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
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banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
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}
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if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
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val = bcm_memc_readl(MEMC_CFG_REG);
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rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
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cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
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is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
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banks = 2;
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}
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/* 0 => 11 address bits ... 2 => 13 address bits */
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rows += 11;
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/* 0 => 8 address bits ... 2 => 10 address bits */
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cols += 8;
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return 1 << (cols + rows + (is_32bits + 1) + banks);
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}
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void __init bcm63xx_cpu_init(void)
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{
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unsigned int tmp, expected_cpu_id;
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struct cpuinfo_mips *c = ¤t_cpu_data;
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unsigned int cpu = smp_processor_id();
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/* soc registers location depends on cpu type */
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expected_cpu_id = 0;
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switch (c->cputype) {
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case CPU_BMIPS3300:
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if ((read_c0_prid() & 0xff00) == PRID_IMP_BMIPS3300_ALT) {
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expected_cpu_id = BCM6348_CPU_ID;
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bcm63xx_regs_base = bcm6348_regs_base;
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bcm63xx_irqs = bcm6348_irqs;
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} else {
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__cpu_name[cpu] = "Broadcom BCM6338";
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expected_cpu_id = BCM6338_CPU_ID;
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bcm63xx_regs_base = bcm6338_regs_base;
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bcm63xx_irqs = bcm6338_irqs;
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}
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break;
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case CPU_BMIPS32:
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expected_cpu_id = BCM6345_CPU_ID;
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bcm63xx_regs_base = bcm6345_regs_base;
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bcm63xx_irqs = bcm6345_irqs;
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break;
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case CPU_BMIPS4350:
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if ((read_c0_prid() & 0xf0) == 0x10) {
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expected_cpu_id = BCM6358_CPU_ID;
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bcm63xx_regs_base = bcm6358_regs_base;
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bcm63xx_irqs = bcm6358_irqs;
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} else {
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/* all newer chips have the same chip id location */
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u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
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switch (chip_id) {
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case BCM6368_CPU_ID:
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expected_cpu_id = BCM6368_CPU_ID;
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bcm63xx_regs_base = bcm6368_regs_base;
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bcm63xx_irqs = bcm6368_irqs;
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break;
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}
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}
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break;
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}
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/*
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* really early to panic, but delaying panic would not help since we
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* will never get any working console
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*/
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if (!expected_cpu_id)
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panic("unsupported Broadcom CPU");
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/*
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* bcm63xx_regs_base is set, we can access soc registers
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*/
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/* double check CPU type */
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tmp = bcm_perf_readl(PERF_REV_REG);
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bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
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bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
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if (bcm63xx_cpu_id != expected_cpu_id)
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panic("bcm63xx CPU id mismatch");
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bcm63xx_cpu_freq = detect_cpu_clock();
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bcm63xx_memory_size = detect_memory_size();
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printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n",
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bcm63xx_cpu_id, bcm63xx_cpu_rev);
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printk(KERN_INFO "CPU frequency is %u MHz\n",
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bcm63xx_cpu_freq / 1000000);
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printk(KERN_INFO "%uMB of RAM installed\n",
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bcm63xx_memory_size >> 20);
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}
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