forked from luck/tmp_suning_uos_patched
9076d0e7e0
On sun4v this is basically required since we point the hypervisor and the TSB walking hardware at these tables using physical addressing too. Signed-off-by: David S. Miller <davem@davemloft.net>
339 lines
7.2 KiB
ArmAsm
339 lines
7.2 KiB
ArmAsm
/* arch/sparc64/kernel/ktlb.S: Kernel mapping TLB miss handling.
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*
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* Copyright (C) 1995, 1997, 2005, 2008 David S. Miller <davem@davemloft.net>
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* Copyright (C) 1996 Eddie C. Dost (ecd@brainaid.de)
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* Copyright (C) 1996 Miguel de Icaza (miguel@nuclecu.unam.mx)
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* Copyright (C) 1996,98,99 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <asm/head.h>
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#include <asm/asi.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/tsb.h>
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.text
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.align 32
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kvmap_itlb:
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/* g6: TAG TARGET */
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_IMMU, %g4
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/* sun4v_itlb_miss branches here with the missing virtual
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* address already loaded into %g4
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*/
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kvmap_itlb_4v:
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kvmap_itlb_nonlinear:
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/* Catch kernel NULL pointer calls. */
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sethi %hi(PAGE_SIZE), %g5
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cmp %g4, %g5
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bleu,pn %xcc, kvmap_dtlb_longpath
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nop
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
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kvmap_itlb_tsb_miss:
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sethi %hi(LOW_OBP_ADDRESS), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_itlb_vmalloc_addr
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mov 0x1, %g5
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sllx %g5, 32, %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_itlb_obp
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nop
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kvmap_itlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g7)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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mov 1, %g7
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sllx %g7, TSB_TAG_INVALID_BIT, %g7
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brgez,a,pn %g5, kvmap_itlb_longpath
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TSB_STORE(%g1, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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/* fallthrough to TLB load */
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kvmap_itlb_load:
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661: stxa %g5, [%g0] ASI_ITLB_DATA_IN
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retry
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_ITLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_itlb_load
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mov %g5, %g3
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kvmap_itlb_longpath:
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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SET_GL(1)
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nop
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.previous
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rdpr %tpc, %g5
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ba,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_ITLB, %g4
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kvmap_itlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_itlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_itlb_load
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nop
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kvmap_dtlb_obp:
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OBP_TRANS_LOOKUP(%g4, %g5, %g2, %g3, kvmap_dtlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_dtlb_load
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nop
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.align 32
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kvmap_dtlb_tsb4m_load:
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TSB_LOCK_TAG(%g1, %g2, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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ba,pt %xcc, kvmap_dtlb_load
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nop
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kvmap_dtlb:
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/* %g6: TAG TARGET */
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mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g4
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/* sun4v_dtlb_miss branches here with the missing virtual
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* address already loaded into %g4
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*/
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kvmap_dtlb_4v:
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brgez,pn %g4, kvmap_dtlb_nonlinear
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nop
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#ifdef CONFIG_DEBUG_PAGEALLOC
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/* Index through the base page size TSB even for linear
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* mappings when using page allocation debugging.
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*/
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
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#else
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/* Correct TAG_TARGET is already in %g6, check 4mb TSB. */
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KERN_TSB4M_LOOKUP_TL1(%g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
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#endif
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/* TSB entry address left in %g1, lookup linear PTE.
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* Must preserve %g1 and %g6 (TAG).
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*/
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kvmap_dtlb_tsb4m_miss:
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/* Clear the PAGE_OFFSET top virtual bits, shift
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* down to get PFN, and make sure PFN is in range.
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*/
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sllx %g4, 21, %g5
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/* Check to see if we know about valid memory at the 4MB
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* chunk this physical address will reside within.
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*/
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srlx %g5, 21 + 41, %g2
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brnz,pn %g2, kvmap_dtlb_longpath
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nop
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/* This unconditional branch and delay-slot nop gets patched
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* by the sethi sequence once the bitmap is properly setup.
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*/
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.globl valid_addr_bitmap_insn
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valid_addr_bitmap_insn:
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ba,pt %xcc, 2f
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nop
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.subsection 2
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.globl valid_addr_bitmap_patch
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valid_addr_bitmap_patch:
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sethi %hi(sparc64_valid_addr_bitmap), %g7
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or %g7, %lo(sparc64_valid_addr_bitmap), %g7
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.previous
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srlx %g5, 21 + 22, %g2
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srlx %g2, 6, %g5
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and %g2, 63, %g2
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sllx %g5, 3, %g5
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ldx [%g7 + %g5], %g5
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mov 1, %g7
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sllx %g7, %g2, %g7
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andcc %g5, %g7, %g0
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be,pn %xcc, kvmap_dtlb_longpath
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2: sethi %hi(kpte_linear_bitmap), %g2
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or %g2, %lo(kpte_linear_bitmap), %g2
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/* Get the 256MB physical address index. */
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sllx %g4, 21, %g5
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mov 1, %g7
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srlx %g5, 21 + 28, %g5
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/* Don't try this at home kids... this depends upon srlx
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* only taking the low 6 bits of the shift count in %g5.
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*/
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sllx %g7, %g5, %g7
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/* Divide by 64 to get the offset into the bitmask. */
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srlx %g5, 6, %g5
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sllx %g5, 3, %g5
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/* kern_linear_pte_xor[((mask & bit) ? 1 : 0)] */
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ldx [%g2 + %g5], %g2
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andcc %g2, %g7, %g0
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sethi %hi(kern_linear_pte_xor), %g5
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or %g5, %lo(kern_linear_pte_xor), %g5
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bne,a,pt %xcc, 1f
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add %g5, 8, %g5
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1: ldx [%g5], %g2
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.globl kvmap_linear_patch
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kvmap_linear_patch:
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ba,pt %xcc, kvmap_dtlb_tsb4m_load
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xor %g2, %g4, %g5
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kvmap_dtlb_vmalloc_addr:
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KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_dtlb_longpath)
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TSB_LOCK_TAG(%g1, %g2, %g7)
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/* Load and check PTE. */
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ldxa [%g5] ASI_PHYS_USE_EC, %g5
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mov 1, %g7
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sllx %g7, TSB_TAG_INVALID_BIT, %g7
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brgez,a,pn %g5, kvmap_dtlb_longpath
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TSB_STORE(%g1, %g7)
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TSB_WRITE(%g1, %g5, %g6)
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/* fallthrough to TLB load */
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kvmap_dtlb_load:
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661: stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Reload TLB
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retry
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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nop
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nop
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.previous
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/* For sun4v the ASI_DTLB_DATA_IN store and the retry
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* instruction get nop'd out and we get here to branch
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* to the sun4v tlb load code. The registers are setup
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* as follows:
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*
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* %g4: vaddr
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* %g5: PTE
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* %g6: TAG
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*
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* The sun4v TLB load wants the PTE in %g3 so we fix that
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* up here.
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*/
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ba,pt %xcc, sun4v_dtlb_load
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mov %g5, %g3
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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kvmap_vmemmap:
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sub %g4, %g5, %g5
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srlx %g5, 22, %g5
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sethi %hi(vmemmap_table), %g1
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sllx %g5, 3, %g5
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or %g1, %lo(vmemmap_table), %g1
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ba,pt %xcc, kvmap_dtlb_load
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ldx [%g1 + %g5], %g5
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#endif
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kvmap_dtlb_nonlinear:
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/* Catch kernel NULL pointer derefs. */
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sethi %hi(PAGE_SIZE), %g5
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cmp %g4, %g5
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bleu,pn %xcc, kvmap_dtlb_longpath
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nop
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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/* Do not use the TSB for vmemmap. */
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mov (VMEMMAP_BASE >> 40), %g5
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sllx %g5, 40, %g5
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cmp %g4,%g5
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bgeu,pn %xcc, kvmap_vmemmap
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nop
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#endif
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KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_dtlb_load)
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kvmap_dtlb_tsbmiss:
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sethi %hi(MODULES_VADDR), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_dtlb_longpath
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mov (VMALLOC_END >> 40), %g5
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sllx %g5, 40, %g5
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cmp %g4, %g5
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bgeu,pn %xcc, kvmap_dtlb_longpath
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nop
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kvmap_check_obp:
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sethi %hi(LOW_OBP_ADDRESS), %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_dtlb_vmalloc_addr
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mov 0x1, %g5
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sllx %g5, 32, %g5
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cmp %g4, %g5
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blu,pn %xcc, kvmap_dtlb_obp
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nop
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ba,pt %xcc, kvmap_dtlb_vmalloc_addr
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nop
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kvmap_dtlb_longpath:
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661: rdpr %pstate, %g5
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wrpr %g5, PSTATE_AG | PSTATE_MG, %pstate
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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SET_GL(1)
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ldxa [%g0] ASI_SCRATCHPAD, %g5
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.previous
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rdpr %tl, %g3
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cmp %g3, 1
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661: mov TLB_TAG_ACCESS, %g4
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ldxa [%g4] ASI_DMMU, %g5
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.section .sun4v_2insn_patch, "ax"
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.word 661b
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ldx [%g5 + HV_FAULT_D_ADDR_OFFSET], %g5
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nop
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.previous
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be,pt %xcc, sparc64_realfault_common
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mov FAULT_CODE_DTLB, %g4
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ba,pt %xcc, winfix_trampoline
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nop
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