forked from luck/tmp_suning_uos_patched
29830c124d
Now that EXPORT_SYMBOL can be used from assembly source, move the EXPORT_SYMBOL invocations for _save_fp & _save_msa to be alongside their definitions. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/14509/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
146 lines
2.7 KiB
ArmAsm
146 lines
2.7 KiB
ArmAsm
/*
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* r2300_switch.S: R2300 specific task switching code.
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*
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* Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
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* Copyright (C) 1994, 1995, 1996 by Andreas Busse
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*
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* Multi-cpu abstraction and macros for easier reading:
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* Copyright (C) 1996 David S. Miller (davem@davemloft.net)
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*
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* Further modifications to make this work:
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* Copyright (c) 1998-2000 Harald Koerfgen
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*/
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#include <asm/asm.h>
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#include <asm/cachectl.h>
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#include <asm/export.h>
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#include <asm/fpregdef.h>
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#include <asm/mipsregs.h>
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#include <asm/asm-offsets.h>
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#include <asm/regdef.h>
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#include <asm/stackframe.h>
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#include <asm/thread_info.h>
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#include <asm/asmmacro.h>
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.set mips1
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.align 5
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/*
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* Offset to the current process status flags, the first 32 bytes of the
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* stack are not used.
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*/
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#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
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/*
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* task_struct *resume(task_struct *prev, task_struct *next,
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* struct thread_info *next_ti)
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*/
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LEAF(resume)
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mfc0 t1, CP0_STATUS
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sw t1, THREAD_STATUS(a0)
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cpu_save_nonscratch a0
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sw ra, THREAD_REG31(a0)
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#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
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PTR_LA t8, __stack_chk_guard
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LONG_L t9, TASK_STACK_CANARY(a1)
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LONG_S t9, 0(t8)
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#endif
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/*
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* The order of restoring the registers takes care of the race
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* updating $28, $29 and kernelsp without disabling ints.
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*/
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move $28, a2
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cpu_restore_nonscratch a1
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addiu t1, $28, _THREAD_SIZE - 32
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sw t1, kernelsp
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mfc0 t1, CP0_STATUS /* Do we really need this? */
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li a3, 0xff01
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and t1, a3
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lw a2, THREAD_STATUS(a1)
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nor a3, $0, a3
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and a2, a3
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or a2, t1
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mtc0 a2, CP0_STATUS
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move v0, a0
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jr ra
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END(resume)
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/*
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* Save a thread's fp context.
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*/
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LEAF(_save_fp)
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EXPORT_SYMBOL(_save_fp)
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fpu_save_single a0, t1 # clobbers t1
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jr ra
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END(_save_fp)
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/*
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* Restore a thread's fp context.
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*/
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LEAF(_restore_fp)
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fpu_restore_single a0, t1 # clobbers t1
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jr ra
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END(_restore_fp)
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/*
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* Load the FPU with signalling NANS. This bit pattern we're using has
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* the property that no matter whether considered as single or as double
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* precision represents signaling NANS.
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*
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* The value to initialize fcr31 to comes in $a0.
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*/
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.set push
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SET_HARDFLOAT
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LEAF(_init_fpu)
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mfc0 t0, CP0_STATUS
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li t1, ST0_CU1
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or t0, t1
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mtc0 t0, CP0_STATUS
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ctc1 a0, fcr31
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li t0, -1
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mtc1 t0, $f0
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mtc1 t0, $f1
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mtc1 t0, $f2
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mtc1 t0, $f3
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mtc1 t0, $f4
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mtc1 t0, $f5
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mtc1 t0, $f6
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mtc1 t0, $f7
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mtc1 t0, $f8
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mtc1 t0, $f9
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mtc1 t0, $f10
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mtc1 t0, $f11
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mtc1 t0, $f12
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mtc1 t0, $f13
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mtc1 t0, $f14
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mtc1 t0, $f15
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mtc1 t0, $f16
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mtc1 t0, $f17
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mtc1 t0, $f18
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mtc1 t0, $f19
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mtc1 t0, $f20
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mtc1 t0, $f21
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mtc1 t0, $f22
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mtc1 t0, $f23
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mtc1 t0, $f24
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mtc1 t0, $f25
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mtc1 t0, $f26
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mtc1 t0, $f27
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mtc1 t0, $f28
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mtc1 t0, $f29
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mtc1 t0, $f30
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mtc1 t0, $f31
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jr ra
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END(_init_fpu)
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.set pop
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