forked from luck/tmp_suning_uos_patched
298476220d
Currently when making changes to control registers, we typically need some time for changes to take effect (8 nops, generally). However, for sh4a we simply need to do an icbi.. This is a simple patch for implementing a general purpose ctrl_barrier() which functions as a control register write barrier. There's some additional documentation in the patch itself, but it's pretty self explanatory. There were also some places where we were not doing the barrier, which didn't seem to have any adverse effects on legacy parts, but certainly did on sh4a. It's safer to have the barrier in place for legacy parts as well in these cases, though this does make flush_tlb_all() more expensive (by an order of 8 nops). We can ifdef around the flush_tlb_all() case for now if it's clear that all legacy parts won't have a problem with this. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
206 lines
4.7 KiB
C
206 lines
4.7 KiB
C
/*
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* Copyright (C) 1999 Niibe Yutaka
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* Copyright (C) 2003 Paul Mundt
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*
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* ASID handling idea taken from MIPS implementation.
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*/
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#ifndef __ASM_SH_MMU_CONTEXT_H
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#define __ASM_SH_MMU_CONTEXT_H
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#ifdef __KERNEL__
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#include <asm/cpu/mmu_context.h>
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#include <asm/tlbflush.h>
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#include <asm/pgalloc.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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/*
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* The MMU "context" consists of two things:
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* (a) TLB cache version (or round, cycle whatever expression you like)
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* (b) ASID (Address Space IDentifier)
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*/
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/*
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* Cache of MMU context last used.
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*/
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extern unsigned long mmu_context_cache;
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#define MMU_CONTEXT_ASID_MASK 0x000000ff
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#define MMU_CONTEXT_VERSION_MASK 0xffffff00
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#define MMU_CONTEXT_FIRST_VERSION 0x00000100
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#define NO_CONTEXT 0
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/* ASID is 8-bit value, so it can't be 0x100 */
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#define MMU_NO_ASID 0x100
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/*
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* Virtual Page Number mask
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*/
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#define MMU_VPN_MASK 0xfffff000
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#ifdef CONFIG_MMU
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/*
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* Get MMU context if needed.
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*/
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static __inline__ void
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get_mmu_context(struct mm_struct *mm)
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{
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extern void flush_tlb_all(void);
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unsigned long mc = mmu_context_cache;
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/* Check if we have old version of context. */
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if (((mm->context ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0)
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/* It's up to date, do nothing */
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return;
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/* It's old, we need to get new context with new version. */
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mc = ++mmu_context_cache;
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if (!(mc & MMU_CONTEXT_ASID_MASK)) {
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/*
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* We exhaust ASID of this version.
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* Flush all TLB and start new cycle.
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*/
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flush_tlb_all();
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/*
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* Fix version; Note that we avoid version #0
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* to distingush NO_CONTEXT.
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*/
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if (!mc)
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mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
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}
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mm->context = mc;
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}
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/*
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* Initialize the context related info for a new mm_struct
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* instance.
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*/
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static __inline__ int init_new_context(struct task_struct *tsk,
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struct mm_struct *mm)
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{
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mm->context = NO_CONTEXT;
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return 0;
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}
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/*
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* Destroy context related info for an mm_struct that is about
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* to be put to rest.
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*/
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static __inline__ void destroy_context(struct mm_struct *mm)
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{
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/* Do nothing */
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}
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static __inline__ void set_asid(unsigned long asid)
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{
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unsigned long __dummy;
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__asm__ __volatile__ ("mov.l %2, %0\n\t"
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"and %3, %0\n\t"
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"or %1, %0\n\t"
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"mov.l %0, %2"
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: "=&r" (__dummy)
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: "r" (asid), "m" (__m(MMU_PTEH)),
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"r" (0xffffff00));
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}
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static __inline__ unsigned long get_asid(void)
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{
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unsigned long asid;
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__asm__ __volatile__ ("mov.l %1, %0"
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: "=r" (asid)
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: "m" (__m(MMU_PTEH)));
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asid &= MMU_CONTEXT_ASID_MASK;
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return asid;
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}
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/*
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* After we have set current->mm to a new value, this activates
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* the context for the new mm so we see the new mappings.
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*/
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static __inline__ void activate_context(struct mm_struct *mm)
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{
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get_mmu_context(mm);
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set_asid(mm->context & MMU_CONTEXT_ASID_MASK);
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}
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/* MMU_TTB can be used for optimizing the fault handling.
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(Currently not used) */
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static __inline__ void switch_mm(struct mm_struct *prev,
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struct mm_struct *next,
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struct task_struct *tsk)
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{
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if (likely(prev != next)) {
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unsigned long __pgdir = (unsigned long)next->pgd;
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__asm__ __volatile__("mov.l %0, %1"
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: /* no output */
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: "r" (__pgdir), "m" (__m(MMU_TTB)));
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activate_context(next);
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}
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev, next) \
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switch_mm((prev),(next),NULL)
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static __inline__ void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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#else /* !CONFIG_MMU */
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#define get_mmu_context(mm) do { } while (0)
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#define init_new_context(tsk,mm) (0)
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#define destroy_context(mm) do { } while (0)
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#define set_asid(asid) do { } while (0)
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#define get_asid() (0)
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#define activate_context(mm) do { } while (0)
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#define switch_mm(prev,next,tsk) do { } while (0)
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) do { } while (0)
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#define enter_lazy_tlb(mm,tsk) do { } while (0)
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#endif /* CONFIG_MMU */
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#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4)
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/*
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* If this processor has an MMU, we need methods to turn it off/on ..
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* paging_init() will also have to be updated for the processor in
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* question.
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*/
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static inline void enable_mmu(void)
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{
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/* Enable MMU */
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ctrl_outl(MMU_CONTROL_INIT, MMUCR);
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ctrl_barrier();
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if (mmu_context_cache == NO_CONTEXT)
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mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
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set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
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}
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static inline void disable_mmu(void)
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{
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unsigned long cr;
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cr = ctrl_inl(MMUCR);
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cr &= ~MMU_CONTROL_INIT;
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ctrl_outl(cr, MMUCR);
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ctrl_barrier();
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}
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#else
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/*
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* MMU control handlers for processors lacking memory
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* management hardware.
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*/
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#define enable_mmu() do { BUG(); } while (0)
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#define disable_mmu() do { BUG(); } while (0)
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#endif
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_MMU_CONTEXT_H */
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