forked from luck/tmp_suning_uos_patched
bca031e2c8
We use "pmc->idx" and the "chained" bitmap to determine if the pmc is
chained, in kvm_pmu_pmc_is_chained(). But idx might be uninitialized
(and random) when we doing this decision, through a KVM_ARM_VCPU_INIT
ioctl -> kvm_pmu_vcpu_reset(). And the test_bit() against this random
idx will potentially hit a KASAN BUG [1].
In general, idx is the static property of a PMU counter that is not
expected to be modified across resets, as suggested by Julien. It
looks more reasonable if we can setup the PMU counter idx for a vcpu
in its creation time. Introduce a new function - kvm_pmu_vcpu_init()
for this basic setup. Oh, and the KASAN BUG will get fixed this way.
[1] https://www.spinics.net/lists/kvm-arm/msg36700.html
Fixes: 80f393a23b ("KVM: arm/arm64: Support chained PMU counters")
Suggested-by: Andrew Murray <andrew.murray@arm.com>
Suggested-by: Julien Thierry <julien.thierry@arm.com>
Acked-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Zenghui Yu <yuzenghui@huawei.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
114 lines
3.8 KiB
C
114 lines
3.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Linaro Ltd.
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* Author: Shannon Zhao <shannon.zhao@linaro.org>
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*/
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#ifndef __ASM_ARM_KVM_PMU_H
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#define __ASM_ARM_KVM_PMU_H
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#include <linux/perf_event.h>
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#include <asm/perf_event.h>
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#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
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#define ARMV8_PMU_MAX_COUNTER_PAIRS ((ARMV8_PMU_MAX_COUNTERS + 1) >> 1)
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#ifdef CONFIG_KVM_ARM_PMU
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struct kvm_pmc {
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u8 idx; /* index into the pmu->pmc array */
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struct perf_event *perf_event;
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};
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struct kvm_pmu {
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int irq_num;
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struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
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DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
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bool ready;
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bool created;
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bool irq_level;
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};
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#define kvm_arm_pmu_v3_ready(v) ((v)->arch.pmu.ready)
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#define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >= VGIC_NR_SGIS)
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx);
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void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val);
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u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
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void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
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void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
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void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
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bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu);
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void kvm_pmu_update_run(struct kvm_vcpu *vcpu);
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void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
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void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
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u64 select_idx);
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bool kvm_arm_support_pmu_v3(void);
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int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr);
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int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu);
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#else
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struct kvm_pmu {
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};
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#define kvm_arm_pmu_v3_ready(v) (false)
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#define kvm_arm_pmu_irq_initialized(v) (false)
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static inline u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx)
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{
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return 0;
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}
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static inline void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu,
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u64 select_idx, u64 val) {}
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static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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static inline void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
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static inline bool kvm_pmu_should_notify_user(struct kvm_vcpu *vcpu)
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{
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return false;
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}
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static inline void kvm_pmu_update_run(struct kvm_vcpu *vcpu) {}
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static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
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static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
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u64 data, u64 select_idx) {}
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static inline bool kvm_arm_support_pmu_v3(void) { return false; }
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static inline int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu,
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struct kvm_device_attr *attr)
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{
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return -ENXIO;
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}
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static inline int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu)
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{
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return 0;
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}
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#endif
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#endif
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