forked from luck/tmp_suning_uos_patched
4267ea72bb
On an arch 2.06 hypervisor, a pending perfmon interrupt will be delivered to the hypervisor at any point the guest is running, regardless of MSR[EE]. In order to reflect this interrupt, the hypervisor has to mask the interrupt in PMGC0 -- and set MSRP[PMMP] to intercept futher guest accesses to the PMRs to detect when to unmask (and prevent the guest from unmasking early, or seeing inconsistent state). This has the side effect of ignoring any changes the guest makes to MSR[PMM], so wait until after the interrupt is clear, and thus the hypervisor should have cleared MSRP[PMMP], before setting MSR[PMM]. The counters wil not actually run until PMGC0[FAC] is cleared in pmc_start_ctrs(), so this will not reduce the effectiveness of PMM. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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| .. | ||
| cell | ||
| backtrace.c | ||
| common.c | ||
| Makefile | ||
| op_model_7450.c | ||
| op_model_cell.c | ||
| op_model_fsl_emb.c | ||
| op_model_pa6t.c | ||
| op_model_power4.c | ||
| op_model_rs64.c | ||