forked from luck/tmp_suning_uos_patched
6f8a444aa6
Have each pxa variant (pxa25x, pxa27x, pxa3xx) have its own device-tree clock initializing function, to be able to register its own specific core clocks. Apply that change specifically to pxa27x. Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Michael Turquette <mturquette@linaro.org>
109 lines
3.4 KiB
C
109 lines
3.4 KiB
C
/*
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* Marvell PXA family clocks
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*
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* Copyright (C) 2014 Robert Jarzmik
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*
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* Common clock code for PXA clocks ("CKEN" type clocks + DT)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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*/
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#ifndef _CLK_PXA_
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#define _CLK_PXA_
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#define PARENTS(name) \
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static const char *name ## _parents[] __initconst
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#define MUX_RO_RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _mux_hw; \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _mux_ops = { \
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.get_parent = name ## _get_parent, \
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.set_parent = dummy_clk_set_parent, \
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}; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk * __init clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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&name ## _mux_hw, &name ## _mux_ops, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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#define RATE_RO_OPS(name, clk_name) \
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static struct clk_hw name ## _rate_hw; \
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static struct clk_ops name ## _rate_ops = { \
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.recalc_rate = name ## _get_rate, \
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}; \
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static struct clk * __init clk_register_ ## name(void) \
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{ \
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return clk_register_composite(NULL, clk_name, \
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name ## _parents, \
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ARRAY_SIZE(name ## _parents), \
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NULL, NULL, \
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&name ## _rate_hw, &name ## _rate_ops, \
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NULL, NULL, CLK_GET_RATE_NOCACHE); \
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}
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/*
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* CKEN clock type
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* This clock takes it source from 2 possible parents :
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* - a low power parent
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* - a normal parent
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*
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* +------------+ +-----------+
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* | Low Power | --- | x mult_lp |
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* | Clock | | / div_lp |\
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* +------------+ +-----------+ \+-----+ +-----------+
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* | Mux |---| CKEN gate |
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* +------------+ +-----------+ /+-----+ +-----------+
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* | High Power | | x mult_hp |/
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* | Clock | --- | / div_hp |
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* +------------+ +-----------+
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*/
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struct desc_clk_cken {
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struct clk_hw hw;
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int ckid;
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const char *name;
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const char *dev_id;
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const char *con_id;
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const char **parent_names;
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struct clk_fixed_factor lp;
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struct clk_fixed_factor hp;
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struct clk_gate gate;
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bool (*is_in_low_power)(void);
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const unsigned long flags;
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};
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#define PXA_CKEN(_dev_id, _con_id, _name, parents, _mult_lp, _div_lp, \
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_mult_hp, _div_hp, is_lp, _cken_reg, _cken_bit, flag) \
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{ .ckid = CLK_ ## _name, .name = #_name, \
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.dev_id = _dev_id, .con_id = _con_id, .parent_names = parents,\
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.lp = { .mult = _mult_lp, .div = _div_lp }, \
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.hp = { .mult = _mult_hp, .div = _div_hp }, \
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.is_in_low_power = is_lp, \
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.gate = { .reg = (void __iomem *)_cken_reg, .bit_idx = _cken_bit }, \
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.flags = flag, \
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}
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#define PXA_CKEN_1RATE(dev_id, con_id, name, parents, cken_reg, \
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cken_bit, flag) \
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PXA_CKEN(dev_id, con_id, name, parents, 1, 1, 1, 1, \
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NULL, cken_reg, cken_bit, flag)
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static int dummy_clk_set_parent(struct clk_hw *hw, u8 index)
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{
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return 0;
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}
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extern void clkdev_pxa_register(int ckid, const char *con_id,
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const char *dev_id, struct clk *clk);
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extern int clk_pxa_cken_init(const struct desc_clk_cken *clks, int nb_clks);
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void clk_pxa_dt_common_init(struct device_node *np);
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#endif
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